Phased array element RF front ends typically use single pole double throw switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, physical size, and performance degradations associated with switches and circulators can present challenges in meeting system performance and SWAP requirements. This paper provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multivariable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the PALNA while maximizing power transfer efficiency and minimizing dissipative losses in each T/R mode of operation. An example design in global foundries 32SOI CMOS at W-band using the proposed methodology is presented. The design achieves simulated maximum power added efficiency of 18% in transmit and noise figure of 7.5 dB in receive at 94 GHz.

This paper examines the concept of multisection capacitive digital-to-analog converters (MS-CDACs), which enables a wider range of CDAC section segmentation options beyond split-CDAC and C-2C methods. In order to study the proposed approach, analysis and simulations are first conducted for all possible section arrangements of a 6-bit resolution MS-CDAC with minimum-sized unit capacitors; the study shows that MSCDAC provides various options with reduced total capacitance compared to a single-section CDAC, and allowing for the tradeoff of area, switching energy, and speed versus static linearity and kT/C noise. Thus, it is possible to find a structure that minimizes total capacitance while satisfying required static linearity and noise that cannot be achieved with the existing methods. Compensation of nonlinearities due to parasitic capacitance is accomplished by sizing the bridge capacitance(s). To verify effectiveness in a more practical design scenario, this approach is applied to a 10-bit MS-CDAC design. Using metal-insulator- metal capacitors available in a standard CMOS technology, under the condition that 95% of Monte Carlo simulation results have at most 0.5 LSB of |DNL|, the selected 10-bit MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively, and MSB capacitance by a factor of 26 relative to the single-section CDAC. The postlayout simulations were also conducted to validate the MS-CDAC approach, achievingmaxin the presence of additional layout parasitics.

This mini workshop is organized to provide an interactive forum for the introduction of a set of five new curriculum modules developed under IEEE's Real World Engineering Projects (RWEP) program. The modules, which are representative of a larger collection of curriculum modules available to the public via an open-access RWEP web portal, are designed for use in the first-year engineering and computer science classroom, and are hands-on, team-based projects that emphasize the societal impact of the work that engineers do. After a brief introduction to the RWEP program and the five showcased curriculum modules, the authors of the modules will work one-on-one with the audience providing tutorials on the laboratory activities associated with their modules in a highly interactive, simultaneous mode.

More than a dozen Wireless @ Virginia Tech faculty are working to address the broad research agenda of cognitive radio and cognitive networks. Our core research team spans the protocol stack from radio and reconfigurable hardware to communications theory to the networking layer. Our work includes new analysis methods and the development of new software architectures and applications, in addition to work on the core concepts and architectures underlying cognitive radios and cognitive networks. This paper describes these contributions and points towards critical future work that remains to fulfill the promise of cognitive radio. We briefly describe the history of work on cognitive radios and networks at Virginia Tech and then discuss our contributions to the core cognitive processing underlying these systems, focusing on our cognitive engine. We also describe developments that support the cognitive engine and advances in radio technology that provide the flexibility desired in a cognitive radio node. We consider securing and verifying cognitive systems and examine the challenges of expanding the cognitive paradigm up the protocol stack to optimize end-to-end network performance. Lastly, we consider the analysis of cognitive systems using game theory and the application of cognitive techniques to problems in dynamic spectrum sharing and control of multiple-input multiple-output radios.

A low-power read-out circuit design for a heterogeneously integrated chemoresistive micro-/nano-sensor arrays is presented. The circuit is based on a sigma delta modulation architecture, to reduce power consumption and to allow for a wider range of resistance measurements. The design and layout of the circuit, in 180nm CMOS is presented, along with measurement results from the prototype IC. The chip successfully reads out resistances ranging from 20kOmega to 600 kOmega with a measured power consumption of 3 mW. The die area occupied by the readout circuit is 180 um times 300 um.

Abstract Networks of the future will be characterized by a variety of computational devices that display a level of dynamism not seen in traditional wired networks. Because of the dynamic nature of these networks, resource discovery is one of the fundamental problems that must be solved. While resource discovery systems are not a novel concept, securing these systems in an efficient and scalable way is challenging. This paper describes the design and implementation of an architecture for access‐controlled resource discovery. This system achieves this goal by integrating access control with the Intentional Naming System (INS), a resource discovery and service location system. The integration is scalable, efficient, and fits well within a proxy‐based security framework designed for dynamic networks. We provide performance experiments that show how our solution outperforms existing schemes. The result is a system that provides secure, access‐controlled resource discovery that can scale to large numbers of resources and users. Copyright © 2004 John Wiley & Sons, Ltd.