In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMC's 0.13-/spl mu/m and TSMC's 0.18-/spl mu/m technologies, the model has an average error of 4.5% and a maximum error of 15%.

In this paper, we propose a new analytical model to estimate the transition time of CMOS inverters, taking into account the main effects of deep submicron (DSM) such as velocity saturation and mobility degradation. The relationship between the input and output transitions is discussed and captured by a closed-form expression. Also, this model has been formulated to depend only on SPICE parameters that are usually provided with the given technology. In other words, neither presimulated extracted parameters nor fitting parameters are required. Thus, the developed model is technology-portable. The proposed model is validated by comparing its results with Spectre simulation results. To ensure the model's robustness, a wide range of output loading and input transition times have been considered. Also, to ensure the model's portability and accuracy for DSM devices, 0.25, 0.18, and 0.13-/spl mu/m technologies have been used to conduct our comparison. Considering the mentioned technologies, the proposed model achieved less than 10% error when it is compared to Specter level 11 (BSIM3v3) simulation results.