A user friendly environment for the fast prototyping of audio bandwidth digital signal processing (DSP) applications and application specific ICs (ASICs) based on reusable hardware components such as FPGAs, microcontrollers, RAMs, DSP-cores, general DSP processors are presented. The paper describes the different target application domains which have been used as drivers for the development of the emulation environment. It describes the approach followed and solutions for real-time emulation of DSP applications. Both the hardware and software aspects are discussed. It summarizes the requirements which have been met by the above system, and gives some ideas on further work to be performed. This development is the result of the ESPRIT project RETIDES (Real Time DSP Emulation System) sponsored by the European Commission.

At the highest abstraction level, the specification of a data path consists of a number of interconnected abstract building blocks and a constraint on the minimal clock frequency. An algorithm which optimally selects hardware blocks for implementing these abstract building blocks is presented. A technique for hierarchical redistribution and insertion of pipeline registers is also presented. Finally, the two optimization tasks are combined. This combination makes the area tradeoff between the cost of additional speedup circuitry and pipeline registers possible. The techniques are based on accurate hierarchical timing models for the hardware blocks. The automation relieves the designer of the numerous, time-consuming critical path verifications and area evaluations that are required to explore the large design space. The implementation of the algorithms has resulted in a CAD tool called HANDEL, embedded in the data-path compiler CHOPIN.>

The goal of this paper is to extend the synthesis of real

A system is presented which automatically generates layout of bit-sliced data paths in high performance DSP circuits. The system consists of a linear placement tool, a track assignment tool and detailed layout tools. In this paper we will present algorithms for linear placement of modules and routing track assignment across the modules. By taking advantage of the inherent structure of the circuits an A* based linear placement algorithm has produced better results compared to a simulated annealing based approach.

Pipelining and hardware selection are important optimization tasks in the design of high-performance data paths. At the highest abstraction level, the specification of a data path consists of a number of interconnected abstract building blocks and a constraint on the minimal required clock frequency. An algorithm which optimally selects hardware blocks from a library for implementing these abstract building blocks is presented, and a technique for hierarchical redistribution and insertion of pipeline registers is described. Finally, both optimization tasks are combined. This combination makes the area tradeoff between additional speed-up circuitry and pipeline registers possible.>

An optimized recursive binary nesting (RBN) algorithm for coding true color documents is presented. The RBN compression in which algorithm is a segmentation algorithm in which a picture is subdivided into regions with equal properties and for each region only the relevant information for the human eye is kept. Thus, the compressed image consists of segmentation information and the information of the picture behavior in those regions. The picture is subsampled on a quadtree based lattice (segmentation information). The inner pixels are approximated with the use of four lattice corner pixels (pictorial behavior). The subdivision in blocks has to be a function of the image contents. The size of the initial blocks is 65*65. Each pixel in the block is approximated as a weighted average of the four corner pixels (bilinear interpolation). The efficient VLSI architecture used to implement the algorithm is termed the lowly multiplexed cooperating data-path style. Several other designs under consideration are briefly reviewed.>

The state of the art of compiling digital signal processing (DSP) algorithms into silicon is discussed. It is indicated how digital signal processing differs from numerical data processing, including the consequences for the synthesis tools. On the basis of a broad range of DSP applications, four classes of architectures are then distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioral DSP specification. The four selected architectural styles are best characterized by hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths, and regular arrays. The characteristics of the first three architectures are treated in more detail in a discussion of three different Cathedral synthesis environments for their respective design. A fourth Cathedral environment, aiming at the synthesis of regular arrays, is still in an early stage of development and is not discussed. The claims for the compilers are substantiated by typical designs.>

A novel methodology is proposed for the data-path definition and assignment for high-throughput front-end audio, image, and video applications. The technique is based on the concept of the identification of application-specific units that can solve the computational bottlenecks of an algorithm in an efficient way. An algorithm for the automatic assignment of operations on these specific units is presented. A test vehicle taken from the video field demonstrates the proposed method.>