This paper is dedicated to the geometry selection of a redundantly actuated cable-suspended parallel robot intended to manipulate heavy payloads over a wide workspace. Cable-suspended refers here to cable-driven parallel robots in a crane-like setting, where all the cable drawing points are located on top of the base frame, gravity being used to keep the cables taut. Geometry selection consists of determining the relative positions of the cable drawing points on the base frame and of the cable attachment points on the mobile platform together with the cable arrangement between these two sets of points. An original performance index is introduced. It is defined as the maximum acceptable distance between the mobile platform geometric center and the center of mass of the set consisting of the platform and a payload. This performance index is of particular interest in heavy payload handling applications. Used within a two-phase geometry selection strategy, it yields a new cable-suspended robot geometry having a very large workspace to footprint ratio and able to handle heavy payloads. A large-dimension redundantly actuated cable-suspended robot was built in order to demonstrate these capabilities.

This paper introduces a new simplified static analysis of parallel robots driven by inextensible cables of non-negligible mass. It is based on a known hefty cable static modeling which seems to have been overlooked in previous works on parallel cable-driven robots. This cable modeling is obtained from a well-known sagging cable modeling, known as the catenary, by assuming that cable sag is relatively small. The use of the catenary has been shown to lead to a non-linear set of equations describing the kinetostatic behavior of parallel robots driven by cables of non-negligible mass. On the contrary, the proposed simplified static analysis yields a linear relationship between (components of) the forces in the cables and the external wrench applied to the robot mobile platform. As a consequence, by means of the simplified static analysis, useful wrench-based analysis and design techniques devised for parallel robots driven by massless cables can now be extended to cases in which cable mass is to be accounted for.

We examine the ability of CMPs, due to their lower on-chip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vector machines. Parallelizing code in this manner leads to a high frequency of barriers, and we explore the impact of different barrier mechanisms upon the efficiency of this approach. To further exploit the potential of CMPs for fine-grained data parallel tasks, we present barrier filters, a mechanism for fast barrier synchronization on-chip multi-processors to enable vector computations to be efficiently distributed across the cores of a CMP. We ensure that all threads arriving at a barrier require an unavailable cache line to proceed, and, by placing additional hardware in the shared portions of the memory subsystem, we starve their requests until they all have arrived. Specifically, our approach uses invalidation requests to both make cache lines unavailable and identify when a thread has reached the barrier. We examine two types of barrier filters, one synchronizing through instruction cache lines, and the other through data cache lines

Energy efficiency of computation is quickly becoming a key problem from the chip through the data center. This paper presents the first quantitative study of the potential energy efficiency of vector accelerators. We propose and study a vector accelerator architecture suitable for implementation in a 70nm technology. The vector architecture has a high-bandwidth on-chip cache system coupled to 16 independent memory channels. We show that such an accelerator can achieve speedups of 10X or more on loop kernels in comparison to a quad-issue superscalar uniprocessor, while using less energy. We also introduce run-ahead lanes, a complexity and energy efficient means of tolerating variable latency from crossbar contention, cache bank conflicts, cache misses, and the memory system. Run-ahead lanes only synchronize on dependencies or when explicitly directed.

This paper offers an overview of the HP Superdome shared memory multiprocessor, along with a detailed description of the cache coherence implementation. (An early and limited description was provided in [9].) We focus in particular on the sx1000 chipset, codenamed Pinnacles, which is used in HP's Integrity line of servers (Superdome Integrity, rx8620, rx7620) and in HP's 9000 series of PA-RISC based products (Superdome. rp8620, rp7420). The design goals for this architecture were to provide a platform that supported both PA-RISC and Itanium family processors, support multiple operating systems including HP-UX, Windows, and Linux, provide cache coherent scalability to large ways of MP. and support multiple product generations while preserving customer investments in memory and I/O infrastructure. This paper covers the system organization and network topology (Section 2), details on how processor instructions appear as coherence transactions (Section 3), the cache coherence protocol (Section 4). and microarchitectural details on the chipset (Section 5). It concludes with examples of application benchmarks that demonstrate the scalability achieved (Section 6).

Inspired by recent advances in microprocessor performance monitors, this paper shows how a shared-memory multiprocessor chipset and interconnect can be equipped with performance monitors that associate performance events with the PCs of the individual instructions causing these events. Such monitors greatly simplify performance debugging of shared-memory programs---for example, they make finding pairs of instructions in false sharing straightforward. These monitors also enable precise feedback-directed compiler optimizations and, as a second contribution, we show how they can guide the code generator to use the version of the load instruction that makes the best use of the coherence protocol. Experiments show up to almost 10% coherence traffic reduction on SPLASH2 applications.

This paper describes scheduling optimizations in the Intel/spl reg/ Itanium/spl reg/ compiler to prevent cache penalties due to various micro-architectural effects on the Itanium 2 processor. This paper does not try to improve cache hit rates but to avoid penalties, which probably all processors have in one form or another, even in the case of cache hits. These optimizations make use of sophisticated methods for disambiguation of memory references, and this paper examines the performance improvement obtained by integrating these methods into the cache optimizations.

Memory expansions are classical means to extract parallelism from imperative programs. However, for dynamic control programs with general memory accesses, such transformations either fail or require some run-time mechanism to restore the data flow. This paper presents an expansion framework for any type of data structure in any imperative program, without the need for dynamic data flow restoration. The key idea is to group together the write operations that participate in the flow of the same datum. We show that such an expansion boils down to mapping each group to a single memory cell. We give a practical algorithm for code transformation. This algorithm, however, is valid for (possibly non-affine) loops over arrays only.

Exact array dataflow analysis can be achieved in the general case if the only control structures are do-loops and structural ifs, and if loop counter bounds and array subscripts are affine expressions of englobing loop counters and possibly some integer constants. In this paper, we begin the study of dataflow analysis of dynamic control programs, where arbitrary ifs and whiles are allowed. In the general case, this dataflow analysis can only be fuzzy.