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Dhruba Basu

dblp:10/6218 · DBLP profile ↗
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7ranked-venue papers
1as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-authorSoftware engineering, systems software and programming languages · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
5 papers
Electronic design automation · 31% Processor architecture and microarchitecture · 24% Distributed systems · 17%

Topics — the 12 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems
fault tolerance
0.011983
Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains · IEEE Trans. Computers 1983
Electronic design automation › hardware verification and test › fault modeling
stuck-at fault model
0.011983
Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains · IEEE Trans. Computers 1983
Hardware reliability and fault tolerance › self-checking circuits
totally self-checking circuits
0.011983
Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains · IEEE Trans. Computers 1983
Electronic design automation
logic synthesis
0.021976
An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words · IEEE Trans. Computers 1976
Multigate Synthesis of General Boolean Functions by Threshold Logic Elements · IEEE Trans. Computers 1969
Integrated circuit design › digital circuit design
arithmetic circuit design
0.011976
On Binary Multiplication Using the Quarter Square Algorithm · IEEE Trans. Computers 1976
Processor architecture and microarchitecture › computer arithmetic
binary multiplication
0.011976
On Binary Multiplication Using the Quarter Square Algorithm · IEEE Trans. Computers 1976
Processor architecture and microarchitecture
microprogramming
0.011976
An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words · IEEE Trans. Computers 1976
Processor architecture and microarchitecture
arithmetic unit
0.011975
On a Simple Postcorrection for Nonrestoring Division · IEEE Trans. Computers 1975
Processor architecture and microarchitecture › division algorithm
nonrestoring division
0.011975
On a Simple Postcorrection for Nonrestoring Division · IEEE Trans. Computers 1975
Integrated circuit design › semiconductor device fabrication
CMOS technology
0.011983
Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains · IEEE Trans. Computers 1983
Electronic design automation › logic synthesis
boolean function decomposition
0.011969
Multigate Synthesis of General Boolean Functions by Threshold Logic Elements · IEEE Trans. Computers 1969
Electronic design automation › logic synthesis
threshold logic synthesis
0.011969
Multigate Synthesis of General Boolean Functions by Threshold Logic Elements · IEEE Trans. Computers 1969

Methods — techniques the papers use, named apart from their topics

redundancy in space and time · 0.0on-line diagnosis · 0.0terminal correction · 0.0quarter square technique · 0.0linear programming · 0.0double precision quotient · 0.0
YearPublicationVenuePosition
1998 Implementation and timing analysis of Clock Synchronization on a transputer-based replicated system
Anupam Sinha, Pradip K. Das, Dhruba Basu
Inf. Softw. Technol.3
1996 Replicated servers for fault-tolerant real-time systems using transputers
Anupam Sinha, Pradip K. Das, Dhruba Basu
Inf. Softw. Technol.3
1983 Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains
abstract
All the totally self checking (TSC) circuits known so far [3]-[8] restrict their fault sets to either single or multiple but unidirectional stuck-at faults. Meyer and Sundstrom [20] have considered on line diagnosis of unrestricted faults but the class of circuits proposed by them does not fall under the category of TSC circuits. This paper proposes a new type of circuit model which is TSC for a fault set, consisting of all possible, i.e., unrestricted stuck-at faults on all the gate input and output signal lines. The model uses redundancy in both space and time domains and realizes combinatorial functions. Some important properties of the model are brought out by a set of lemmas and theorems. The viability of the model is demonstrated by a circuit example which uses CMOS technology.
K. V. S. S. Prasad Rao, Dhruba Basu
IEEE Trans. Computers2
1976 On Binary Multiplication Using the Quarter Square Algorithm
abstract
This correspondence suggests a new method of perporming binary multiplication using the quarter square technique. As compared to the previous methods [1],[2] the proposed scheme is more general in that it can be readily applied to numbers of any word length. Moreover, it has been shown that for the eight-bit case the present method is faster, more systematic, and economical than the earlier schemes.
Totadri Jayashree, Dhruba Basu
IEEE Trans. Computers2
1976 An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words
abstract
This paper suggests a new method for minimizing the width or bit dimension of control store words in microprogrammed digital computers. It is shown that any given problem can be formulated within the framework of linear programming and that there exists a lower limit CLB to the number of bits. The optimal grouping of subcommands which gives this minimal width is also readily obtainable.
Totadri Jayasri, Dhruba Basu
IEEE Trans. Computers2
1975 On a Simple Postcorrection for Nonrestoring Division
abstract
This correspondence points out that the usual terminal correction for nonrestoring division can always be made in such a way as to permit concatenation of the primary and secondary quotients to form a double precision answer. This eliminates the necessity of any separate postcorrection as suggested in [1] and [2].
Dhruba Basu, Totadri Jayashree
IEEE Trans. Computers1
1969 Multigate Synthesis of General Boolean Functions by Threshold Logic Elements
abstract
A decomposition and reconstruction approach for synthesizing an arbitrary Boolean function with a minimum number of threshold logic elements connected by feedforward paths only is presented. Attention is mainly focused on cascade-type realizations. The approach has the advantage that near-minimal solutions are readily derived. An estimate of how closely the minimality has been approached is obtainable in this method. The method has been successfully applied by the authors to Boolean functions of 5 and 6 variables.
Sukumar Ghosh, Dhruba Basu, Arun K. Choudhury
IEEE Trans. Computers2