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Michael Faiman

dblp:11/242 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 3Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
3 papers
Routing and switching · 74% Internet architecture and protocols · 26%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
Interconnection networks and networks-on-chip · 58% Integrated circuit design · 42%

Topics — the 11 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Routing and switching › routing algorithms
shortest path routing
0.021991
Load-Sharing and Shortest-Path Routing in Transparently Interconnected Local Area Networks · INFOCOM 1991
A New Responsive Distributed Shortest-Path Rounting Algorithm · SIGCOMM 1989
Internet architecture and protocols › network interconnection
LAN interconnection
0.011991
Load-Sharing and Shortest-Path Routing in Transparently Interconnected Local Area Networks · INFOCOM 1991
Routing and switching
load sharing
0.011991
Load-Sharing and Shortest-Path Routing in Transparently Interconnected Local Area Networks · INFOCOM 1991
Internet architecture and protocols › local area network
transparent bridge
0.011991
Load-Sharing and Shortest-Path Routing in Transparently Interconnected Local Area Networks · INFOCOM 1991
Routing and switching › switch architecture
nonblocking switch design
0.011990
Pulsa: Non-Blocking Packet Switching with Shift-Register Rings · SIGCOMM 1990
Routing and switching
packet switching
0.011990
Pulsa: Non-Blocking Packet Switching with Shift-Register Rings · SIGCOMM 1990
Routing and switching
switch architecture
0.011990
Pulsa: Non-Blocking Packet Switching with Shift-Register Rings · SIGCOMM 1990
Interconnection networks and networks-on-chip › switching
high-speed switching
0.011990
Pulsa: Non-Blocking Packet Switching with Shift-Register Rings · SIGCOMM 1990
Routing and switching › routing protocol
distance-vector routing
0.011989
A New Responsive Distributed Shortest-Path Rounting Algorithm · SIGCOMM 1989
Integrated circuit design
digital circuit design
0.011973
B73-11 Digital Circuits and Devices · IEEE Trans. Computers 1973
Integrated circuit design › digital circuit design
logic design
0.011973
B73-11 Digital Circuits and Devices · IEEE Trans. Computers 1973

Methods — techniques the papers use, named apart from their topics

spanning tree protocol · 0.0ford-fulkerson algorithm · 0.0
YearPublicationVenuePosition
1991 Load-Sharing and Shortest-Path Routing in Transparently Interconnected Local Area Networks
abstract
A new transparent bridging scheme, called the source dependent spanning tree (SDS), is presented in which bridges observe broadcast packets from active hosts to create the shortest path trees for these hosts dynamically. Issues related to packet forwarding in the presence of multiple trees are identified and algorithms for addressing these issues are presented. Some important properties of SDS, such as correctness, are described, and it is compared with previously proposed schemes. Under standard traffic assumptions, it is shown that SDS can achieve load sharing and shortest-path routing without incurring excessive storage and communication overheads.>
Bala Rajagopalan, Michael Faiman
INFOCOM2
1990 Pulsa: Non-Blocking Packet Switching with Shift-Register Rings
abstract
This paper discusses the design of a switch for high-speed computer networking at gigabit rates. We present the Pulsar switch, a non-blocking design based on a high-spin-rate, port-dedicated, word-parallel, shift-register ring. Several design alternatives address the problem of Head-Of-Line blocking. In contrast to Batcher-Banyan switches, access to the ring is asynchronous which facilitates low delay and arbitrary packet length. The switch can support ATM cells simultaneously with packets sized for applications such as single characters, memory words, disk blocks, memory pages, or video images. Pulsar can be used as a high-throughput computer backplane replacement. The design can be implemented with existing high-speed circuit technology.
Gary J. Murakami, Roy H. Campbell, Michael Faiman
SIGCOMM3
1989 A New Responsive Distributed Shortest-Path Rounting Algorithm
abstract
Distributed shortest-path routing algorithms based on the Ford-Fulkerson method are simple to implement but they suffer from the cost-dependent looping problem: when link costs increase, routing table loops may form and convergence to correct paths may be too slow, depending on link costs. This problem can be eliminated if constraints are imposed on the order in which routing tables are updated at different nodes but the resulting internode protocols tend to be relatively complex. Furthermore, update constraints may restrict a node's ability to obtain alternate paths quickly in an environment where topology changes are frequent. In this paper, a new distributed shortest-path routing scheme based on the Ford-Fulkerson method is presented. Under the new scheme, each node uses partial topology information to eliminate the cost-dependent looping problem. No update constraints are imposed and no assumptions are made regarding link costs. In the worst case, the new scheme responds to link cost changes in O(D) update steps, where D is the diameter of the network after the occurrence of the changes.
Bala Rajagopalan, Michael Faiman
SIGCOMM2
1987 Distributed Global Event Synchronization in a Fiber Optic Hypergraph Network
Yoram Ofek, Michael Faiman
ICDCS2
1973 B73-11 Digital Circuits and Devices
abstract
This book comprises two distinct parts. The first five chapters form a standard exposition on logic design, while the remainder, which is of about the same length as the first part, deals with digital electronics. Each chapter is followed by a set of problems and references, and a lengthy bibliography is included as an Appendix.
Michael Faiman
IEEE Trans. Computers1