A novel technique for the stabilization of local oscillators is presented in this paper based on the combination of a Phase Locked Loop (PLL) and Delay Locked Loop (DLL) architecture. On one hand, phase noise performances are improved taking advantage of the both architecture and more particular to the non-accumulation of random timing jitter. On the other hand, such a methodology could relax constraints on the loop filter and it would then be possible to increase the architecture bandwidth without taking care of stability drawbacks. By the way, the settling time could be largely improved.

This paper presents a 65 nm CMOS power amplifier (PA) using a coupled transformer. The PA is based on an original structure, called stacked folded fully differential structure (SFFDS). It is applied to the UMTS W-CDMA standard. The parallel SFFDS power amplifier provides 30.5 dBm of output power with 20% of power added efficiency (PAE) at 1.95 GHz. The output compression point (OCP1) is 27.5 dBm and the PA is linear up to 24 dBm in order to meet the maximum output power required by the UMTS W-CDMA standard.

ldquoMore than Moorerdquo is becoming the password for these coming years. New steps to overcome technology limitations to diffuse, on the same die, different chips to have a complete system have been developed. This approach is called system in package (SiP), a way to have in a package dies of logic, analog, memory, passive components, etc., assembled to obtain a miniaturized board. SiP performances and limitations are here analyzed to understand advantages versus system on chip (SoC). This paper is a discussion about the main items that can lead to the choice of the right approach-SiP or SoC-before a system design start. Three persons attend to our virtual meeting: an SoC technology development manager, expert in microcontroller embedded memories and technology integration; an SiP analog radio-frequency design senior expert; and a moderator that designed embedded memories and now SiP, all involved to understand how to reach a tradeoff among these two approaches. Like for the Yin and Yang, symbol of the equilibrium for the Taoist philosophy, the two opposites divide the circle of the life, with a piece of each in the other.

This paper investigates the feasibility of designing a RF TX architecture based on a Power VCO, operating at 1.95 GHz for UMTS/WCDMA standard. The Power VCO uses 2.5 V supply voltage and is designed using 65 nm CMOS technology from ST Microelectronics. The Power VCO is made up of an oscillating Power Amplifier (PA). In order to fulfil UMTS/W-CDMA requirements, especially on output power with regards to efficiency to save battery life, the used PA is a two-stage Class E PA. The output 1 dB compression point (CP1) is 22 dBm and Power Added Efficiency (PAE) @CP1 is 55.1%. This PA is then included in a loop to realize oscillation condition. The Power VCO oscillates @ 1.95 GHz, achieves an output power of 23.3 dBm with 60.3% PAE.

This paper presents how noninteger order filters can be used in phase locked loop (PLL) based frequency synthesizers in order to increase their stability robustness. Application to a 192MHz PLL involved in a 3.6GHz multimode double loop frequency synthesizer is described

Summary form only given. Accurately predicting the impact of substrate parasitics in Radio Frequency (RF) design with simulations is one of the major concerns to ensure first silicon success in a System on Chip (SoC) approach. The practical design experience of a 2 GHz RF front-end circuit (designed in a 0.35 /spl mu/m SiGe BiCMOS technology), presented here, illustrates how measurements results can be accurately predicted using a substrate parasitic extractor.