The diversity of contextual information is of great importance for accurate semantic segmentation. However, most methods focus on single spatial contextual information, which results in an overlap of the semantic content of categories and a loss of contour information of objects. In this article, we propose a novel contour knowledge-aware perception learning network (CKPL-Net) to capture diverse contextual information by space-category aggregation module (SCAM) and contour-aware calibration module (CACM). First, SCAM is introduced to enhance intraclass consistency and interclass differentiation of features. By integrating space-aware and category-aware attention, SCAM reduces the redundancy of features from a categorical perspective while maintaining spatial correlation of pixels, substantially avoiding the overlap of the semantic content in categories. Second, CACM is designed to maintain the integrity of objects by perceiving contour contextual information. It develops a novel contour-aware knowledge and adaptively transforms the grid structure of convolutions for boundary pixels, which effectively calibrates the representation of features near boundaries. Finally, the quantitative and qualitative analyses on the three public datasets: ISPRS Potsdam dataset, ISPRS Vaihingen dataset, and WHDLD dataset, demonstrate that the proposed CKPL-Net achieves superior performance compared with prevalent methods, which indicates diverse contextual information is beneficial for accurate segmentation.

BACKGROUND: N6-methyladenosine (m6A) and 5-methylcytosine (m5C) are the main RNA methylation modifications involved in the oncogenesis of cancer. However, it remains obscure whether m6A/m5C-related long non-coding RNAs (lncRNAs) affect the development and progression of low grade gliomas (LGG). METHODS: We summarized 926 LGG tumor samples with RNA-seq data and clinical information from The Cancer Genome Atlas and Chinese Glioma Genome Atlas. 105 normal brain samples with RNA-seq data from the Genotype Tissue Expression project were collected for control. We obtained a molecular classification cluster from the expression pattern of sreened lncRNAs. The least absolute shrinkage and selection operator Cox regression was employed to construct a m6A/m5C-related lncRNAs prognostic signature of LGG. In vitro experiments were employed to validate the biological functions of lncRNAs in our risk model. RESULTS: The expression pattern of 14 sreened highly correlated lncRNAs could cluster samples into two groups, in which various clinicopathological features and the tumor immune microenvironment were significantly distinct. The survival time of cluster 1 was significantly reduced compared with cluster 2. This prognostic signature is based on 8 m6A/m5C-related lncRNAs (GDNF-AS1, HOXA-AS3, LINC00346, LINC00664, LINC00665, MIR155HG, NEAT1, RHPN1-AS1). Patients in the high-risk group harbored shorter survival times. Immunity microenvironment analysis showed B cells, CD4 + T cells, macrophages, and myeloid-derived DC cells were significantly increased in the high-risk group. Patients in high-risk group had the worse overall survival time regardless of followed TMZ therapy or radiotherapy. All observed results from the TCGA-LGG cohort could be validated in CGGA cohort. Afterwards, LINC00664 was found to promote cell viability, invasion and migration ability of glioma cells in vitro. CONCLUSION: Our study elucidated a prognostic prediction model of LGG by 8 m6A/m5C methylated lncRNAs and a critical lncRNA regulation function involved in LGG progression. High-risk patients have shorter survival times and a pro-tumor immune microenvironment.

For remote sensing image segmentation, the boundaries of objects are difficult to distinguish, which is ignored by most methods. Therefore, it is challenging how to excavate and recover the boundaries of objects accurately. In this article, we propose a boundary-aware multi-scale network (BMNet) to solve this problem. The key components of BMNet include the scale attention module (SA-module) and boundary guidance module (BG-module). Specifically, SA-module is proposed to guide the refinement of multi-scale features in a context-aware way. It enhances the discriminability of multi-scale features by establishing contextual dependencies, which enables the refinement of the prediction of objects. Then, BG-module is proposed to enable networks to distinguish the boundary of objects. It utilizes manifold information of features to generate boundary guidance maps and forces the network to focus more on the boundary of objects. The effectiveness of the proposed BMNet is demonstrated on two public remote sensing datasets: ISPRS 2-D semantic labeling Potsdam dataset and Vaihingen dataset, where BMNet achieves better segmentation than prevalent methods. Finally, the experimental results indicate that BMNet can produce sharper boundaries of objects to reconstruct more detailed segmentation results.

In this paper, we discuss the advantages and opportunities presented by high-speed (> 50 GHz) reconfigurable integrated circuits and how they may drive reconfigurable systems applications, such as software-defined radio, radar, and imaging. We propose silicon-germanium (SiGe) BiCMOS as an example technology that enables ultrafast reconfigurable systems and present several circuit designs based on SiGe heterojunction bipolar transistors (HBTs). We compare circuit designs between generations of IBM's SiGe process, including a recent 9HP process featuring devices with a cutoff frequency (fT) of 300 GHz. We describe an architecture for an 8-b 80-Gs/s analog-to-digital converter (ADC) and a 48 × 48 cell field programmable gate array (FPGA), which provide powerful solutions for useful functions, such as digital signal processing (DSP) and polyphase filtering. Other circuit concepts are described, including a voltage-controlled oscillator (VCO) with a tuning range of 26 GHz and a high-performance (80 Gb/s) crossbar switch, which provide utility in reconfigurable system applications. Measured results from fabricated implementations of these described systems are presented. We comment on future prospects of these systems and examine an emerging lateral bipolar device (fT1/4 825 GHz) having 100x less power consumption than conventional vertical HBTs.

Off-The-Shelf (COTS) software components have been extensively used by applications over the world. However, COTS components always carry issues that might and sometimes only take place at runtime, in particular, when combined with other components. This might bring serious trouble for the application's dependability. Based on the industry experiences that lots of faulty components usually occupy excessive resources, this paper proposes an approach to localize the faulty components in an application automatically through analyzing the resource usage of components. Once a faulty component interferes with the application's performance, our approach generates an anomaly report, localizes the faulty component, and enables component level recovery to remove the negative impact. We have implemented a prototype and demonstrated its effectiveness on the well-known JPetStore benchmark with performance overhead of less than 3%.

Service Level Agreements (SLAs) play an important role in service-based systems. However, traditional approaches to establish SLAs are mostly manual and predefined which is not suitable for the highly dynamic and unpredictable service-oriented environment. In this paper, we propose a policy-based framework for supporting dynamic and automated SLA negotiations for Web services. In our framework, we extend the WS-Policy framework to provide a domain-independent policy language for specifying QoS constraints over the QoS attributes that are to be negotiated. Negotiation agents are dynamically created to perform SLA negotiations on behalf of each negotiating party in a P2P way using standard web services invocations. Decision making models of negotiation agents are also defined in a declarative way and can be reconfigured easily. We have implemented a prototype of our framework and demonstrated our approach through a case study.

Internetware is proposed as a new software paradigm to cope with the open, dynamic and ever-changing Internet environment for applications. The incarnated characteristics of Internetware promote the operating platform to be more dynamic and adaptable. As an operating platform, PKUAS (Peking University Application Server) has been successfully applied in various fields. However, its inexplicit module boundary, insufficient lifecycle management and absent dependency management, make it hardly meet challenges. In this paper we refactor PKUAS into PKUAS II by introducing OSGi (Open Services Gateway Initiative) to achieve a better dynamic capability. First, PKUAS II adopts service component oriented model as its structure so that the boundary among modules can be explicitly explained, and the continuous lifecycle management and dynamic dependency management can get supported. PKUAS II is able to upgrade without interruption of service and extend on the fly with new services. Second, PKUAS II supports application--aware customization, which can dynamically generate a just enough application server for the application at runtime, to satisfy different applications' requirements and reduce resource costs. Last but not least, some evaluations have been done, which show that PKUAS II is more flexible and dynamic without significant performance overhead, and might support Internetware better.

Abstract Many data‐gathering protocols for wireless sensor networks use clustering technology for prolonging network lifetime. Cluster‐based protocols reduce the total energy consumption via data aggregation and balance energy consumption via clusterhead rotation. However, most existing protocols focus on load balance within each cluster. The energy consumption of the entire network is still unbalanced and this uneven energy dissipation can significantly reduce network lifetime. We propose an even energy dissipation protocol (EEDP) for efficient cluster‐based data gathering in wireless sensor networks. In EEDP, sensor data are forwarded to the base station (BS) via multiple chains of clusterheads. Each chain uses a rotation scheme to balance energy consumption among clusterheads and avoid the formation of a hot spot. We developed efficient algorithms to organize clusterheads into multiple chains, such that the traffic load is evenly distributed among different chains. Analysis and simulation results show that EEDP achieves better load balance than several existing protocols and significantly increases network lifetime. Copyright © 2007 John Wiley & Sons, Ltd.

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

Many data gathering protocols for wireless sensor networks use clustering technology for prolonging the network lifetime. Cluster-based protocols reduce the total energy consumption via data aggregation, and balance energy consumption via clusterhead rotation. However, most existing protocols focus on load balance within each cluster. The energy consumption of the entire network is still unbalanced, and this uneven energy dissipation can significantly reduce the network lifetime. We propose an even energy dissipation protocol (EEDP) for efficient cluster-based data gathering in wireless sensor networks. In EEDP, the sensor data are forwarded to the base station via multiple chains of clusterheads. Each chain uses a rotation scheme to balance energy consumption among clusterheads and avoid the formation of a hot spot. We developed efficient algorithms to organize clusterheads into multiple chains, such that the traffic load is evenly distributed among different chains. Analysis and simulation results show that EEDP achieves better load balance than several existing protocols and significantly increases network lifetime

FPGAs have been a popular topic among electrical engineers for over a decade. Modern FPGAs are denser, faster and use less power compared to PLD and CPLD. This paper presents a high speed FPGA that operates in the gigahertz range. An improved reconfigurable circuit is described. State-of-the-art IBM SiGe BiCMOS technology is used to realize this high speed FPGA. A measurement on a fabricated chip proves that this FPGA is capable of operating at 11 GHz, a SONET OC-192 standard, for optical applications.

This paper describes the implementation of a large scale SiGe FPGA that serves as a high speed FPGA test platform. In the FPGA core, 20 x 20 building blocks (Basic Cells) are used to implement logic applications. This chip contains 106 devices including SiGe NPNs and MOSFETs. This chip is fabricating with the IBM SiGe 7HP process with cut off frequency of 120GHz. The target running frequency of this FPGA is 10GHz. Clock repeaters are added for improved clock distribution. A test circuit whose building block cell runs up to 10GHz is fabricated and measured by the same process. Future work and some potential applications of the SiGe FPGA are also described.

This paper describes the implementation of a scalable SiGe FPGA that serves as a high speed FPGA test platform. A new configurable block (Basic Cell) has been evolved from the Xilinx 6200 specification, and is designed to perform in the gigahertz range. Two chips, a 4:1 multiplexer and 1:4 demultiplexer, were designed using the IBM SiGe 7HP process. The two designs can process 10 Gbps data streams.

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit's performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.

The low operating speed of current CMOS Field Programmable Gate Arrays (FPGAs), i.e., 10-220 MHz, has prevented their use in high-speed digital applications. With the advent of IBM Silicon Germanium (SiGe) 7HP technology, designers have been able to design FPGAs operating in the gigahertz range. This paper is going to elaborate on the implementation of a 4-bit ripple-carry full adder (FA) on the new SiGe FPGA with new architectures and a novel power management strategy. The 1-bit FA can be realized in three Configurable Logic Blocks (CLBs). Apart from these, the FA can operate in multiple modes: FAST, NON-CRITICAL, SLOW and OFF. The propagation delays of the 1-bit FA and 4-bit ripple-carry FA are 240 ps and 675 ps respectively in the FAST mode. All the simulation and layouts were done using Cadence 4.4.6 and IBM SiGe 7HP design kit version 1.1.1.0.

A high speed, low power FPGA design is presented in this paper. This gigahertz FPGA design has an improved XC6200 structure. Redundant multiplexers are eliminated from critical signal path to enhance the performance of the previous design. By balancing between the power consumption and performance, the simulated clock rate is from 5 GHz to 20 GHz and the power consumption is from 4 mW to 12 mW per single cell in the IBM 7HP SiGe HBT BiCMOS process.

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.