A unified design representation can work. This has always been considered impractical due to major problems of run time, space, tool interdependencies, and multiple representations. We have addressed these problems and found them tractable. We present our solutions to these problems, gained through the experience of developing the Droid design system.

CLAY takes a netlist partitioned down to the transistor level, a technology file with an arbitrary number of metal layers, and constraints on aspect and I/O signal positions to produce mask geometries. CLAY attempts to capture, in software, layout knowledge at the transistor level (allowing variable-shaped cells including heights) and at the floorplan level for VLSI sized examples. CLAY compares well with standard cell and manual approaches.>

The authors report a quantitative comparison of area evaluation metrics for CMOS transistor placement, along with a novel analysis technique to determine their absolute merit. The transistor placer TOPOLOGIZER was used to generate test case placements. The resolution of transistor placement algorithms based on metrics (e.g. simulated annealing, branch and bound) are limited to the resolution of the metric. The best metric studied was only able to correctly identify, with 90% accuracy, the better of two placements whose layout areas differed by more than 30%.>