In this paper, we describe the software environment for Daytona, a single-chip, bus-based, shared-memory, multiprocessor DSP.The software environment is designed around a layered architecture.Tools at the lower layer are designed to deliver maximum performance and include a compiler, debugger, simulator, and profiler.Tools at the higher layer focus on improving the programmability of the system and include a run-time kernel and parallelizing tools.The run-time kernel includes a low-overhead, preemptive, dynamic scheduler with multiprocessor support that guarantees real-time performance to admitted tasks.1.

The authors suggest a parallel processing structure using the proposed international standard for visual telephony (CCITT P*64 kbs standard) as processing elements, to compress digital high definition television (HDTV) pictures. The basic idea is to partition an HDTV picture, in space or in frequency, into smaller sub-pictures and then compress each sub-picture using a CCITT P*64 kbs coder. This seems to be a cost-effective solution to the HDTV hardware. Since each sub-picture is processed by an independent coder, without coordination these coded sub-pictures may have unequal picture quality. To maintain a uniform quality HDTV picture, the following two issues are studied: sub-channel control strategy (bits allocated to each sub-picture); and quantization and buffer control strategy for individual sub-picture coders. Algorithms to resolve these problems and their computer simulations are presented.>

High Definition Television (HDTV) promises to offer wide-screen, much better quality pictures as compared to the today’s television. However, without compression a digital HDTV channel may cost up to one Gbits/sec transmission bandwidth. We suggest a parallel processing structure using the proposed international standard for visual telephony (CCITT Px64 kbs standard) as processing elements, to compress the digital HDTV pictures. The basic idea is to partition an HDTV picture into smaller sub-pictures and then compress each sub-picture using a CCITT Px64kbs coder, which is cost-effective, by today’s technology, only on small size pictures. Since each sub-picture is processed by an independent coder, without coordination these coded sub-pictures may have unequal picture quality. To maintain a uniform quality HDTV picture, the following two issues are studied: (l) sub-channel control strategy (bits allocated to each sub-picture), and (2) quantization and buffer control strategy for individual sub-picture coder. Algorithms to resolve the above problems and their computer simulations are presented.

Future video services in the loop plant may be based on digital transmission through optical fibers. A small and inexpensive codec is required for a variety of services based on digital television. We have demonstrated a compression algorithm for transmission of NTSC color television over a DS3 channel (44.736 Mbits/s). This predictive coding algorithm has been implemented using circuits built with conventional TTL logic. The resulting picture is visually unimpaired, but may not have network quality. The major portion of the compression or reconstruction circuit has also been implemented in one CMOS VLSI chip. Compression is accomplished using this chip with two small ROM chips. Reconstruction is done with the same VLSI chip and one ROM chip.