Shared Virtual Environments (SVEs) have been extensively researched for education, entertainment, work, and training, yet there has been limited research on the creative aspects of collaboration in SVEs. This raises questions about how to design virtual working spaces to support collaborative creativity in SVEs. In this paper, we outline an SVE named LeMo, which allows two people to create music collaboratively. Then we present a study of LeMo, in which 42 users composed music together using three different virtual working space configurations. Results indicate that (i) two types of territory and working configurations emerged during collaborative composing (ii) when made available to them, personal working spaces were extensively used, and were considered to be essential to successful collaborative music making and (iii) a publicly visible personal working space was preferable to a publicly invisible one. Based on these findings, three corresponding design implications for Shared Virtual Environments focusing on supporting collaborative creativity are given.

In recent years, Virtual Reality (VR) applications have become widely available. An increase in popular interest raises questions about the use of the new medium for communication. While there is a wide variety of literature regarding scene transitions in films, novels and computer games, transitions in VR are not yet widely understood. As a medium that requires a high level of immersion [2], transitions are a desirable tool. This poster delineates an experiment studying the impact of transitions on user experience of presence in VR.

Flash-based Solid-State Drives (SSDs) are data storage devices that use flash memory to store persistent data. Previously we presented a centralized on-board cache for SSDs to improve the response time and reduce the physical writes to the flash media. An automatic periodic update (APU) feature with fixed period is used to write dirty and stable cache lines to flash media when the SSD is idle. In this work we propose a distributed on-board cache architecture to match the intrinsic parallelism of SSDs. Since there are N individual flash packages in one SSD device, N dirty cache lines are selected by the APU feature, each of which is written to a separate flash package. Simulation results show that this distributed on-board cache can significantly reduce the response time of SSDs by up to 90% compared with the SSDs without such a cache, while reducing the number of physical writes to the flash memory.