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George A. Zimmerman

dblp:119/4749 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Physical-layer communications · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Physical-layer communications › signal processing for communications
quantization
0.011995
Spur-reduced digital sinusoid synthesis · IEEE Trans. Commun. 1995
Physical-layer communications
signal generation
0.011995
Spur-reduced digital sinusoid synthesis · IEEE Trans. Commun. 1995
Integrated circuit design › analog and mixed-signal circuits › data converters
digital-to-analog converter
0.011995
Spur-reduced digital sinusoid synthesis · IEEE Trans. Commun. 1995

Methods — techniques the papers use, named apart from their topics

spectral analysis · 0.0quantization theory · 0.0
YearPublicationVenuePosition
1995 Spur-reduced digital sinusoid synthesis
abstract
This paper presents and analyzes a technique for reducing the spurious signal content in digital sinusoid synthesis. Spur reduction is accomplished through dithering amplitude and phase values prior to wordlength reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output wordlength reduction without introducing additional spurs. Effects of periodic dither similar to that produced by a pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M+1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise can be made white, making the noise power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution.>
Michael J. Flanagan, George A. Zimmerman
IEEE Trans. Commun.2
1992 Analysis of I/O efficient order-statistic-based noise power estimators
abstract
Order-statistic-based noise power estimators for constant false alarm rate (CFAR) detection are considered in terms of required estimator accuracy and estimator dynamic range. By limiting the dynamic range of the value to be estimated, the performance of an order statistic estimator can be achieved by simple threshold-and-count techniques requiring only a single pass of the data. Noise power estimation in the Search for Extraterrestrial Intelligence (SETI) microwave observing project sky survey is considered as an example CFAR application. By using several parallel threshold-and-count estimation devices, the dynamic range can be expanded to meet SETI system requirements, with minimal hardware complexity. A second order-statistic-based estimator with wider dynamic range, but greater complexity is also examined.>
George A. Zimmerman, Edward Olsen
ICASSP1