This paper describes the error performance of the ISDN basic access digital subscriber line (DSL), the high bit rate digital subscriber line (HDSL), and the asymmetric digital subscriber line (ADSL) in the presence of impulse noise. Results are found by using data from the 1986 NYNEX impulse noise survey in simulations. It is shown that a simple uncoded ADSL would have an order of magnitude more errored seconds than DSL and HDSL.>

Asymmetric digital subscriber line (ADSL) is an emerging technology for the transport of asymmetric DS1-rate services over a single copper twisted-pair in the local loop plant. One of the key ingredients to the ADSL system is the upstream low bit-rate control channel. The architecture and laboratory implementation of the low bit-rate upstream control channel is described. The system was first computer modeled, and then the transmitter/receiver were implemented around programmable digital signal processing chips (DSP) such as the TI TMS320C40. Experimental results indicate that the system is functional to loops of 18 kft.>

An innovative digital timing recovery method for synchronous digital receivers is described. This method is based on estimating the impulse response of the channel and then choosing an optimal sampling phase from this estimate. The method uses an adaptive transversal filter (TF), operating at the baud rate and driven by a decision-directed reference, to cancel the sampled received far-end signal. This timing recovery technique connects, in a natural way, with receivers using decision feedback equalizers (DFEs). A 30-tap DFE receiver incorporating this timing recovery scheme has been simulated and implemented in real time on a single DSP (digital signal processor).>

The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. The architecture and accuracy studies for finite-wordlength processing are discussed. The chip was implemented, tested, and found to be fully functional. Possible variations are presented for multipurpose (variable transform sizes, forward-backward transform) applications.>

The circuit switching fabric for broadband networks will demand numerous densely interconnected components, with channel rates as high as 150 Mbit/s, This is a natural application area for VLSI, which motivates the evaluation of the key technologies and requirements for realizable broadband circuit and packet switching systems. The critical circuit switching capabilities include the basic crosspoint array, I/O interface between circuit packs, jitter removal and regeneration, and multichannel phase alignment. This paper describes results obtained in these four critical areas. With remote multiplexing units, the greatest constraints are power dissipation and system volume. CMOS circuitry has the advantage here, because of its intrinsic usage-sensitive low power operation. The challenge is to prove that CMOS processes and designs are compatible with the high data and clock rates required of broadband ISDN systems. A fully connected 16 × 16 crosspoint array has been implemented by several laboratories. In this paper we will report on our asynchronous 16 × 16 switching chips fabricated in a 2 μm CMOS process. These devices support channel rates of up to 240 Mbit/s. Crosstalk, jitter accumulation, and power dissipation dominate system issues at the IC interface, making simple CMOS or TTL signaling inappropriate for broadband applications. We will discuss the ECL compatible signaling used in our broadband CMOS IC's. This low noise interface is currently operating at 150-200 MHz rates. We will stress the resulting improvement in noise and jitter accumulation. We will also consider a broader class of low power signaling schemes, including CMOS to GaAsFET direct interfacing. The physical design of switching fabric components will be at least as important as the electronics. Our custom high-density chip carrier and surface mounting arrangement will be discussed, which offers a fourfold reduction in parasitic inductance and capacitance, with corresponding reductions in crosstalk, jitter, and interconnect power dissipation. Pulses normally degrade after passing through asynchronous crosspoint elements. A scalable switching fabric must include regeneration to control this accumulated noise and jitter. We have demonstrated the critical components of such a regenerator, including VCO's, process independent digital phase shifters, phase error detectors, and data relocking circuitry. Existing CMOS technology can support the circuit switching requirements for broadband networks. A thorough understanding of the interface capabilities and requirements will be necessary to deliver functional hardware. The knowledge gained in this work will have direct application to packet switch constraints and performance.