High-speed elementary function generation is crucial to the performance of many DSP applications. This paper presents three new architectures for generating elementary functions with IEEE single precision using second-order interpolation. These designs have been developed through a combination of architectural innovations and algorithm developments. They represent a range of trade-off between the use of memory modules and computational circuits. Our most memory intensive architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuitry.

High speed elementary function generation is crucial to the performance of many DSP applications. The paper presents an interpolator architecture for generating elementary functions based on an optimal trade off between the use of memory modules and computational circuits. The architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuit. The pipelined design has a throughput of generating one functional value per clock cycle, and a latency of two clock cycles.

This paper describes the design of a 16/spl times/16 complex-number multiplier developed as part of the arithmetic datapath of a complex-number digital signal processor. The complex-number multiplier internally uses binary signed digits for fast multiplication and compact layout. It employs the traditional three-multiplication scheme while minimizing the logic and delay associated with the three extra pre-multiplication binary additions which that scheme requires. The minimization comes from producing the redundant binary sum for each of the pre-multiplication binary additions with minimal hardware, and then recoding the redundant sums as radix-4 multiplier operands. The radix-4 operands halve the number of summands to be added in each of the three real multiplier units. Furthermore, an additional factor of two reduction in the number of summands is effectuated by our coding scheme for representing binary signed digits. The result is a fast and compact complex-number multiplier.>

Huffman coding, a variable-length entropy coding scheme, is an integral component of international standards on image and video compression including high-definition television (HDTV). The high-bandwidth HDTV systems of data rate in excess of 100 Mpixels/s presents a challenge for designing a fast and economic circuit for intrinsically sequential Huffman decoding operations. This paper presents an algorithm and a circuit implementation for parallel decoding of programmable Huffman codes by using the numerical properties of Huffman codes. The 1.2 /spl mu/m CMOS implementation for a single JPEG AC table of 256 codewords of up to 16-b codeword lengths is estimated to run at 10 MHz with a chip area of 11 mm/sup 2/, decoding one codeword per cycle. The design can be pipelined to deliver a throughput of 80 MHz for decoding input streams of consecutive Huffman codes. Furthermore, our programmable scheme can be easily integrated into data paths of video processors to support different Huffman tables used in image/video applications.>

The adoption of MPEG-2 (Motion Pictures Experts Group) by the FCC as the HDTV video compression and transport methodologies laid the foundation for merging multimedia, broadcasting and telecommunication applications. The MPEG-2 video standard, frozen in Nov. 93, supports data rates above 10 Mpbs, real-time transmission, and progressive and interlaced scan sources. This tutorial describes the basic components of an MPEG-2 based HDTV compression system including video formats, color space transformation and decimation, motion estimation and compensation, discrete cosine transform, and variable-length coding. The frame-based and field-based motion estimation schemes required for interlaced scan sources are described in detail. Also discussed is the specific profile and level targeting HDTV application in the MPEG-2 standard.>

Huffman coding is an integral component of international standards on image and video compression including high-definition television (HDTV). The high-bandwidth HDTV systems of data rate in excess of 100 Mpixels/sec presents a challenge for designing a fast and economic circuit for intrinsically sequential Huffman decoding operations. The paper presents an algorithm and a circuit implementation for parallel decoding of programmable Huffman codes by using the numerical properties of Huffman codes. The 1.2 /spl mu/m CMOS implementation for a single JPEG AC table of 256 codewords of up to 16-bit codeword lengths is estimated to run at 40 MHz with a chip area of 11 mm/sup 2/, decoding one codeword per cycle. The design can be pipelined to deliver a throughput of 80 MHz for decoding input streams of consecutive Huffman codes. Furthermore, the programmable scheme can be easily integrated into data paths of video processors to support different Huffman tables used in image/video applications.>

Image compression applications use vector quantization (VQ) for its high compression ratio and image quality. The current VQ hardware employs static instead of dynamic code book generation as the latter demands intensive computation and corresponding expensive hardware even though it offers better image quality. This paper describes a VLSI architecture for a real-time dynamic code book generator and encoder of 512/spl times/512 images at 30 frames/s. The four-chip 0.8 /spl mu/m CMOS design implements a tree of Kohonen self-organizing maps, and consists of two VQ processors and two image buffer memory chips. The pipelined VQ processor contains a computational core for both code book generation and encoding, and is scalable to processing larger frames.>

A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS.>

Article Free Access Share on Systolic implementations of a move-to-front text compressor Authors: C. D. Thomborson Computer Science Department, University of Minnesota, 10 University Drive, Duluth, Minnesota Computer Science Department, University of Minnesota, 10 University Drive, Duluth, MinnesotaView Profile , B. W.-Y. Wei Department of Electrical Engineering, San Jose State University, 1 Washington Square, San Jose, California Department of Electrical Engineering, San Jose State University, 1 Washington Square, San Jose, CaliforniaView Profile Authors Info & Claims SPAA '89: Proceedings of the first annual ACM symposium on Parallel algorithms and architecturesMarch 1989 Pages 283–290https://doi.org/10.1145/72935.72965Published:01 March 1989Publication History 5citation274DownloadsMetricsTotal Citations5Total Downloads274Last 12 Months8Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The authors present a procedure for computing the cycle time of concurrent systems modeled by a restricted class of Petri nets, i.e. decision-free and safe persistent nets. The procedure is based on formulating the cycle time computation as a minimal cost-to-time ratio cycle problem. The result is an efficient algorithm with a computational complexity of O(n/sup 3/log/sub 2/ n). By using an example with a stochastic counterpart, it is shown that the results are consistent with those obtained by more complex Markov analysis.>