Demo Data from SIGIR 2026 / reviewers in the wild / expert
Preston Briggs
dblp:12/5312
· DBLP profile ↗
10ranked-venue papers
6as first author
0since 2021 · last 2015
0000-0001-7217-3793ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 7 · 6 first-authorSystems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Memory systems · 41% Parallel and multicore computing · 37% Storage systems · 14% | |
| Software engineering, system software, and programming languages
5 papers |
Compilers and program optimization · 100% |
Topics — the 19 heaviest of 20, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
parallel programming models |
0.2 | 3 | 2014 | Alembic: automatic locality extraction via migration · OOPSLA 2014 Early Experience with Scientific Programs on the Cray MTA-2 · SC 2003 Tera Hardware Software Cooperation · SC 1997 |
Memory systems › shared memory
distributed shared memory |
0.2 | 1 | 2015 | Latency-Tolerant Software Distributed Shared Memory · USENIX ATC 2015 |
Memory systems › shared memory › distributed shared memory
software distributed shared memory |
0.2 | 1 | 2015 | Latency-Tolerant Software Distributed Shared Memory · USENIX ATC 2015 |
Storage systems
data migration |
0.2 | 1 | 2014 | Alembic: automatic locality extraction via migration · OOPSLA 2014 |
Parallel and multicore computing › parallel programming models › distributed memory programming models
partitioned global address space |
0.2 | 1 | 2014 | Alembic: automatic locality extraction via migration · OOPSLA 2014 |
Memory systems
shared memory |
0.1 | 1 | 2015 | Latency-Tolerant Software Distributed Shared Memory · USENIX ATC 2015 |
Memory systems
data movement |
0.1 | 1 | 2014 | Alembic: automatic locality extraction via migration · OOPSLA 2014 |
Parallel and multicore computing › parallel programming models
multithreaded programming |
0.0 | 1 | 2003 | Early Experience with Scientific Programs on the Cray MTA-2 · SC 2003 |
High-performance computing › scientific computing systems
scientific application portability |
0.0 | 1 | 2003 | Early Experience with Scientific Programs on the Cray MTA-2 · SC 2003 |
High-performance computing
scientific computing systems |
0.0 | 1 | 2003 | Early Experience with Scientific Programs on the Cray MTA-2 · SC 2003 |
Compilers and program optimization › register allocation
graph coloring register allocation |
0.0 | 3 | 1994 | Improvements to Graph Coloring Register Allocation · ACM Trans. Program. Lang. Syst. 1994 Rematerialization · PLDI 1992 Coloring Heuristics for Register Allocation · PLDI 1989 |
Compilers and program optimization
register allocation |
0.0 | 3 | 1994 | Improvements to Graph Coloring Register Allocation · ACM Trans. Program. Lang. Syst. 1994 Rematerialization · PLDI 1992 Coloring Heuristics for Register Allocation · PLDI 1989 |
Processor architecture and microarchitecture
multithreading |
0.0 | 1 | 1997 | Tera Hardware Software Cooperation · SC 1997 |
Parallel and multicore computing › parallel programming models
shared-memory parallelization |
0.0 | 1 | 1997 | Tera Hardware Software Cooperation · SC 1997 |
Performance modeling and evaluation
benchmarking |
0.0 | 1 | 2003 | Early Experience with Scientific Programs on the Cray MTA-2 · SC 2003 |
Compilers and program optimization › compiler analysis › value numbering
global value numbering |
0.0 | 1 | 1994 | Effective Partial Redundancy Elimination · PLDI 1994 |
Compilers and program optimization › compiler optimization › redundancy elimination
partial redundancy elimination |
0.0 | 1 | 1994 | Effective Partial Redundancy Elimination · PLDI 1994 |
Compilers and program optimization › register allocation
spill code minimization |
0.0 | 1 | 1989 | Coloring Heuristics for Register Allocation · PLDI 1989 |
Compilers and program optimization › parallel program optimization
compiler optimization for parallel architectures |
0.0 | 1 | 1997 | Tera Hardware Software Cooperation · SC 1997 |
Methods — techniques the papers use, named apart from their topics
latency tolerance · 0.2migration · 0.2performance measurement · 0.0optimistic coloring heuristic · 0.0global value numbering · 0.0global reassociation · 0.0graph coloring · 0.0graph coloring heuristics · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Latency-Tolerant Software Distributed Shared Memory
Jacob Nelson 0001, Brandon Holt, Brandon Myers, Preston Briggs, Luis Ceze, Simon Kahan, Mark Oskin |
USENIX ATC | 4 |
| 2014 | Alembic: automatic locality extraction via migrationabstractPartitioned Global Address Space (PGAS) environments simplify writing parallel code for clusters because they make data movement implicit - dereferencing global pointers automatically moves data around. However, it does not free the programmer from needing to reason about locality - poor placement of data can lead to excessive and even unnecessary communication. For this reason, modern PGAS languages such as X10, Chapel, and UPC allow programmers to express data-layout constraints and explicitly move computation. This places an extra burden on the programmer, and is less effective for applications with limited or data-dependent locality (e.g., graph analytics). Brandon Holt, Preston Briggs, Luis Ceze, Mark Oskin |
OOPSLA | 2 |
| 2003 | Early Experience with Scientific Programs on the Cray MTA-2abstractWe describe our experiences porting and tuning three scientific programs to the Cray MTA-2, paying particular attention to the problems posed by I/O. We have measured the performance of each of the programs over many different machine configurations and we report on the scalability of each program. In addition, we compare the performance of the MTA with that of an SGI Origin running all three programs. Wendell Anderson, Preston Briggs, C. Stephen Hellberg, Daryl W. Hess, Alexei M. Khokhlov, Marco Lanzagorta, Robert Rosenberg |
SC | 2 |
| 1998 | Practical Improvements to the Construction and Destruction of Static Single Assignment FormabstractStatic Single Assignment (SSA) form is a program representation that is becoming increasingly popular for compiler-based code optimization. In this paper, we address three problems that have arisen in our use of SSA form. Two are variations to the SSA construction algorithms presented by Cytron et al.1 The first variation is a version of SSA form that we call ‘semi-pruned’ SSA. It offers an attractive trade-off between the cost of global data-flow analysis required to build ‘pruned’ SSA and the large number of unused ϕ-functions found in minimal SSA. The second variation speeds up the program renaming process by efficiently manipulating the stacks of names used during renaming. Our improvement reduces the number of pushes performed, in addition to more efficiently locating the stacks that should be popped. To convert code in SSA form back into an executable form, the compiler must use an algorithm that replaces ϕ-functions with appropriately-placed copy instructions. The algorithm given by Cytron et al. for inserting copies produces incorrect results in some situations; particularly in cases like instruction scheduling, where the compiler may not be able to split ‘critical edges’, and in the aftermath of optimizations that aggressively rewrite the name space, like some forms of global value numbering.2 We present a new algorithm for inserting copy instructions to replace ϕ-functions. It fixes the problems that we have encountered with the original copy insertion algorithm. We present experimental results that demonstrate the effectiveness of the first two improvements not only during the construction of SSA form, but also in the time saved by subsequent optimization passes that use a smaller representation of the program. © 1998 John Wiley & Sons, Ltd. Preston Briggs, Keith D. Cooper, Timothy J. Harvey, L. Taylor Simpson |
Softw. Pract. Exp. | 1 |
| 1997 | Tera Hardware Software CooperationabstractThe development of Tera's MTA system was unusual. It respected the need for fast hardware and large shared memory, facilitating execution of the most demanding parallel application programs. But at the same time, it met the need for a clean machine model enabling calculated compiler optimizations and easy programming; and the need for novel architectural features necessary to support fast parallel system software. From its inception, system and application needs have molded the MTA architecture. The result is a system that offers high performance and ease of programming by virtue not only of fast physical hardware and flat shared memory, but also of the streamlined software systems that well utilize the features of the architecture intended to support them. Gail A. Alverson, Preston Briggs, Susan Coatney, Simon Kahan, Richard Korry |
SC | 2 |
| 1997 | Value NumberingabstractValue numbering is a compiler-based program analysis method that allows redundant computations to be removed. This paper compares hash-based approaches derived from the classic local algorithm1 with partitioning approaches based on the work of Alpern, Wegman and Zadeck.2 Historically, the hash-based algorithm has been applied to single basic blocks or extended basic blocks. We have improved the technique to operate over the routine's dominator tree. The partitioning approach partitions the values in the routine into congruence classes and removes computations when one congruent value dominates another. We have extended this technique to remove computations that define a value in the set of available expressions (AVAIL).3 Also, we are able to apply a version of Morel and Renvoise's partial redundancy elimination4 to remove even more redundancies. The paper presents a series of hash-based algorithms and a series of refinements to the partitioning technique. Within each series, it can be proved that each method discovers at least as many redundancies as its predecessors. Unfortunately, no such relationship exists between the hash-based and global techniques. On some programs, the hash-based techniques eliminate more redundancies than the partitioning techniques, while on others, partitioning wins. We experimentally compare the improvements made by these techniques when applied to real programs. These results will be useful for commercial compiler writers who wish to assess the potential impact of each technique before implementation. © 1997 John Wiley & Sons, Ltd. Preston Briggs, Keith D. Cooper, L. Taylor Simpson |
Softw. Pract. Exp. | 1 |
| 1994 | Effective Partial Redundancy EliminationabstractPartial redundancy elimination is a code optimization with a long history of literature and implementation. In practice, its effectiveness depends on issues of naming and code shape. This paper shows that a combination of global reassociation and global value numbering can increase the effectiveness of partial redundancy elimination. By imposing a discipline on the choice of names and the shape of expressions, we are able to expose more redundancies. Preston Briggs, Keith D. Cooper |
PLDI | 1 |
| 1994 | Improvements to Graph Coloring Register AllocationabstractWe describe two improvements to Chaitin-style graph coloring register allocators. The first, optimistic coloring , uses a stronger heuristic to find a k -coloring for the interference graph. The second extends Chaitin's treatment of rematerialization to handle a larger class of values. These techniques are complementary. Optimistic coloring decreases the number of procedures that require spill code and reduces the amount of spill code when spilling is unavoidable. Rematerialization lowers the cost of spilling some values. This paper describes both of the techniques and our experience building and using register allocators that incorporate them. It provides a detailed description of optimistic coloring and rematerialization. It presents experimental data to show the performance of several versions of the register allocator on a suite of FORTRAN programs. It discusses several insights that we discovered only after repeated implementation of these allocators. Preston Briggs, Keith D. Cooper, Linda Torczon |
ACM Trans. Program. Lang. Syst. | 1 |
| 1992 | RematerializationabstractThis paper examines a problem that arises during global register allocation – rematerialization. If a value cannot be kept in a register, the allocator should recognize when it is cheaper to recompute the value (rematerialize it) than to store and reload it. Chaitin's original graph-coloring allocator handled simple instance of this problem correctly. This paper details a general solution to the problem and presents experimental evidence that shows its importance. Preston Briggs, Keith D. Cooper, Linda Torczon |
PLDI | 1 |
| 1989 | Coloring Heuristics for Register AllocationabstractWe describe an improvement to a heuristic introduced by Chaitin for use in graph coloring register allocation. Our modified heuristic produces better colorings, with less spill code. It has similar compile-time and implementation requirements. We present experimental data to compare the two methods. Preston Briggs, Keith D. Cooper, Ken Kennedy, Linda Torczon |
PLDI | 1 |