The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high density memory devices. However, cost of writing or programming Flash memories is an order of magnitude higher than traditional memories. In this paper, we design an algorithm to reduce both average write energy and latency in Flash memories. We achieve this by reducing the number of expensive '01' and '10' bit-patterns during error control coding. We show that the algorithm does not change the error correction capability and moreover improves endurance. Simulations results on representative bit-stream traces show that the use of the proposed algorithm saves, on average, 33% of write energy and 31% of latency of Intel MLC NOR Flash memory, and improves the endurance by 24%.

Voltage scaling has proven to be very effective in reducing the power consumption of digital systems. However, voltage overscaling, ie., reducing the voltage below the critical voltage, introduces errors which have to be compensated by additional computations. In this paper, we propose the use of radix-2 redundant binary arithmetic (RBR) as an alternative for designing low power robust systems. We show that for large data widths, such systems have superior energy-delay product (EDP) and error performance compared to 2's complement based systems. However, for smaller data widths, the 2's complement system has better EDP performance, and in such cases, we propose a low complexity prediction technique to compensate for voltage overscaled errors. We evaluate the performance of the RBR system and the 2's complement system for two image processing kernels, namely, the Gaussian filter and DCT/IDCT. We show that the RBR system is the low power design choice for the Gaussian filter with 16 bits precision while the 2's complement system with most significant bit prediction is the low power design choice for the IDCT kernel.