Demo Data from SIGIR 2026 / reviewers in the wild / expert
John Eisenlohr
dblp:121/2431
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
High-performance computing · 45% GPUs and heterogeneous computing · 31% Parallel and multicore computing · 24% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Theoretical computer science
1 paper |
Graph algorithms and graph theory · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing › GPU computing › GPU sparse computation
GPU sparse linear algebra |
0.2 | 1 | 2014 | Fast Sparse Matrix-Vector Multiplication on GPUs for Graph Applications · SC 2014 |
High-performance computing › sparse linear algebra › sparse matrix computation
sparse matrix-vector multiplication |
0.2 | 1 | 2014 | Fast Sparse Matrix-Vector Multiplication on GPUs for Graph Applications · SC 2014 |
Compilers and program optimization › parallelization
inspector-executor |
0.1 | 1 | 2012 | Code generation for parallel execution of a class of irregular loops on distributed memory systems · SC 2012 |
Compilers and program optimization › code generation
parallel code generation |
0.1 | 1 | 2012 | Code generation for parallel execution of a class of irregular loops on distributed memory systems · SC 2012 |
Parallel and multicore computing › parallelization strategies
distributed-memory parallelization |
0.1 | 1 | 2012 | Code generation for parallel execution of a class of irregular loops on distributed memory systems · SC 2012 |
High-performance computing › scientific computing systems
climate modeling |
0.0 | 1 | 2012 | Code generation for parallel execution of a class of irregular loops on distributed memory systems · SC 2012 |
High-performance computing
scientific computing |
0.0 | 1 | 2012 | Code generation for parallel execution of a class of irregular loops on distributed memory systems · SC 2012 |
Methods — techniques the papers use, named apart from their topics
static and runtime analysis · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | A model-driven blocking strategy for load balanced sparse matrix-vector multiplication on GPUs
Arash Ashari, Naser Sedaghati, John Eisenlohr, P. Sadayappan |
J. Parallel Distributed Comput. | 3 |
| 2014 | An efficient two-dimensional blocking strategy for sparse matrix-vector multiplication on GPUsabstractSparse matrix-vector multiplication (SpMV) is one of the key operations in linear algebra. Overcoming thread divergence, load imbalance and non-coalesced and indirect memory access due to sparsity and irregularity are challenges to optimizing SpMV on GPUs. Arash Ashari, Naser Sedaghati, John Eisenlohr, P. Sadayappan |
ICS | 3 |
| 2014 | Fast Sparse Matrix-Vector Multiplication on GPUs for Graph ApplicationsabstractSparse matrix-vector multiplication (SpMV) is a widely used computational kernel. The most commonly used format for a sparse matrix is CSR (Compressed Sparse Row), but a number of other representations have recently been developed that achieve higher SpMV performance. However, the alternative representations typically impose a significant preprocessing overhead. While a high preprocessing overhead can be amortized for applications requiring many iterative invocations of SpMV that use the same matrix, it is not always feasible -- for instance when analyzing large dynamically evolving graphs. This paper presents ACSR, an adaptive SpMV algorithm that uses the standard CSR format but reduces thread divergence by combining rows into groups (bins) which have a similar number of non-zero elements. Further, for rows in bins that span a wide range of non zero counts, dynamic parallelism is leveraged. A significant benefit of ACSR over other proposed SpMV approaches is that it works directly with the standard CSR format, and thus avoids significant preprocessing overheads. A CUDA implementation of ACSR is shown to outperform SpMV implementations in the NVIDIA CUSP and cuSPARSE libraries on a set of sparse matrices representing power-law graphs. We also demonstrate the use of ACSR for the analysis of dynamic graphs, where the improvement over extant approaches is even higher. Arash Ashari, Naser Sedaghati, John Eisenlohr, Srinivasan Parthasarathy 0001, P. Sadayappan |
SC | 3 |
| 2012 | Code generation for parallel execution of a class of irregular loops on distributed memory systemsabstractParallelization and locality optimization of affine loop nests has been successfully addressed for shared-memory machines. However, many large-scale simulation applications must be executed in a distributed-memory environment, and use irregular/sparse computations where the control-flow and array-access patterns are data-dependent. In this paper, we propose an approach for effective parallel execution of a class of irregular loop computations in a distributed-memory environment, using a combination of static and runtime analysis. We discuss algorithms that analyze sequential code to generate an inspector and an executor. The inspector captures the data-dependent behavior of the computation in parallel and without requiring complete replication of any of the data structures used in the original computation. The executor performs the computation in parallel. The effectiveness of the framework is demonstrated on several benchmarks and a climate modeling application. Mahesh Ravishankar, John Eisenlohr, Louis-Noël Pouchet, J. Ramanujam, Atanas Rountev, P. Sadayappan |
SC | 2 |