The paper discusses the data flow and buffer management for an integrated ASIC performing the high level data link control (HDLC) protocol processing functions for large number of multi-rate (n/spl times/64 kbps) and/or sub-rate (p/spl times/8 kbps) logical channels supported over time division multiplexing (TDM) network interfaces. The highly integrated ASICs are sought-out by the original equipment manufacturers (OEMs) to meet the growing demand for port and connection density. The integration, however, poses a significant challenge for ASIC developers in managing the large number of data flows. Thus, a data flow and buffer management mechanism is required for efficiently managing the data flows so as to maximize the utilization of the network bandwidth and minimize the data loss. The design and analysis of such a mechanism is addressed. The mechanism implementation encompasses both the host and ASIC domains, however, the host domain design is given emphasis in the paper. The critical parameters in the sub-system are identified and characterized utilizing the simulation model. A prototype is built for the host domain in the network driver interface specifications (NDIS) framework in the form of a kernel mode device driver on a generic computing platform. The mechanism was tested satisfactorily with the programmable ASIC device that consists of an embedded reduced instruction set computer (RISC) processor and many significant features suitable for TDM based telecommunications and data communications applications.

The generalized type-II hybrid automatic repeat request (ARQ) scheme on Markov channels is examined in order to study the effect of feedback channel errors on the performance of ARQ systems. It is shown that it is possible to derive expressions for certain critical performance parameters, such as the throughput efficiency, the probabilities of packet loss, undetected error, and correct delivery. To provide a means of comparison, a parallel set of expressions is provided under the usual assumption of an error-free feedback channel. By use of simulations, the ARQ system performance is examined under noiseless feedback and noisy feedback. It is found that feedback channel noise can result in the loss of packets, an increase in the number of undetected errors, and the occurrence of unnecessary transmissions. To enhance the performance of the GH-II ARQ scheme, a predictor is used and found to lower the probability of undetected error, reduce the number of unnecessary transmissions, and increase the throughput efficiency. >

A generalized hybrid automatic-repeat-request (GH-ARQ) scheme using hard-decision decoding and variable depth (redundancy) for adaptive error control in digital communications systems has recently been proposed by S.D. Morgera and H. Krishna (see Digital Signal Processing over Finite Fields: Applications to Communications and Algebraic Coding Theories. New York: Academic, 1988). An important feature of the GH-ARQ scheme is that variable depth and, consequently, variable minimum distance, is possible with a single encoder/decoder configuration. The present authors use binary PSK signaling, an additive white Gaussian noise (AWGN) channel, and several relevant code parameter choices in computer simulations to illustrate the improvement in throughput efficiency when soft-decision decoding is used in the GH-ARQ method. From the computational complexity standpoint, the use of GH-ARQ soft-decision decoding is feasible, since the code lengths used are relatively short. Comparison of simulation results is also made to the soft-decision ARQ scheme of G. Benelli (see ibid., vol.COM-33, p.285-8, Mar. 1985).>