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Claes Thelander

dblp:122/4257 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2010
0000-0002-9794-1864ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › emerging device technologies
nanowire FET
0.112010
III-V Nanowires - Extending a Narrowing Road · Proc. IEEE 2010
Integrated circuit design
semiconductor devices
0.112010
III-V Nanowires - Extending a Narrowing Road · Proc. IEEE 2010
Integrated circuit design › semiconductor devices
heterostructure devices
0.012010
III-V Nanowires - Extending a Narrowing Road · Proc. IEEE 2010
Integrated circuit design › semiconductor devices › semiconductor device design
transistor design
0.012010
III-V Nanowires - Extending a Narrowing Road · Proc. IEEE 2010

Methods — techniques the papers use, named apart from their topics

top-down processing · 0.1bottom-up growth · 0.1
YearPublicationVenuePosition
2010 III-V Nanowires - Extending a Narrowing Road
abstract
Semiconductor nanowires have attracted considerable attention during the last decade and are considered as an alternative path to extend the road for scaled semiconductor devices. The interest is motivated by the improved electrostatic control in the cylindrical geometry and the possibility to utilize heterostructures in transistor design. Currently, nanowire transistors have been realized both in III-Vs and in group IV materials employing top-down as well as bottom-up technologies. In this review, we give an overview of the field and, in particular, we summarize state-of-the-art for III-V nanowire devices. It is demonstrated that the growth and processing technologies are maturing and that devices with good transistor characteristics are being fabricated by a combined bottom-up and top-down approach. Also, the first radio-frequency (RF)-implementations are reviewed and discussed.
Lars-Erik Wernersson, Claes Thelander, Erik Lind, Lars Samuelson
Proc. IEEE2