Demo Data from SIGIR 2026 / reviewers in the wild / expert
Peter S. Y. Lau
dblp:122/6564
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 100% | |
| Computer networks
1 paper |
Routing and switching · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › permutation network
batcher-banyan network |
0.0 | 1 | 1992 | Design and analysis of a multilink access subsystem based on the Batcher-banyan network architecture · IEEE Trans. Commun. 1992 |
Interconnection networks and networks-on-chip
switching network |
0.0 | 1 | 1992 | Design and analysis of a multilink access subsystem based on the Batcher-banyan network architecture · IEEE Trans. Commun. 1992 |
Routing and switching
packet switch |
0.0 | 1 | 1992 | Design and analysis of a multilink access subsystem based on the Batcher-banyan network architecture · IEEE Trans. Commun. 1992 |
Methods — techniques the papers use, named apart from their topics
asymptotic performance analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Design and analysis of a multilink access subsystem based on the Batcher-banyan network architectureabstractA multilink access subsystem based on the Batcher-banyan network architecture is proposed. With this subsystem, multiple physical output links connecting a pair of switching nodes can be shared in an effective way. The subsystem is also configurational so that there is no restriction on any particular partition of physical output links. This is accomplished by executing the proposed multilink access algorithm on a modified Batcher sorter. It is shown that the required hardware can be integrated into the Batcher sorter, and the multilink access algorithm can be integrated with the contention resolution three-phase algorithm. The overhead incurred due to the running of the multilink access algorithm is calculated and the asymptotic performance analyses of the resulting single queue multilink access switch are presented. Results show that the proposed architecture has higher capacity than the unilink access counterpart, has low delay, and has low packet loss probability with small buffer size.> Peter S. Y. Lau, Alberto Leon-Garcia |
IEEE Trans. Commun. | 1 |