Demo Data from SIGIR 2026 / reviewers in the wild / expert
Chitchanok Chuengsatiansup
dblp:124/1916
· DBLP profile ↗
22ranked-venue papers
7as first author
15since 2021 · last 2026
0000-0002-0329-2681ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 18 · 6 first-author · 11 since 2021Software engineering, systems software and programming languages · 3 · 3 since 2021Systems, architecture and hardware · 2 · 2 since 2021Theory of computation · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
12 papers |
Hardware security and side channels · 62% Cryptographic primitives and cryptanalysis · 15% Privacy and data protection · 9% | |
| Computer architecture, parallel and distributed computing, and storage systems
6 papers |
Processor architecture and microarchitecture · 90% Memory systems · 10% | |
| Software engineering, system software, and programming languages
3 papers |
Compilers and program optimization · 58% Programming languages and type systems · 29% Program verification · 12% |
Topics — the 29 heaviest of 29, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
microarchitectural side channel |
3.1 | 4 | 2026 | Fish and Chips: On the Root Causes of Co-Located Website-Fingerprinting Attacks · IEEE Trans. Dependable Secur. Comput. 2026 Testing Side-channel Security of Cryptographic Implementations against Future Microarchitectures · CCS 2024 BunnyHop: Exploiting the Instruction Prefetcher · USENIX Security Symposium 2023 |
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack |
2.2 | 3 | 2025 | Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants) · ASPLOS (2) 2025 Ultimate SLH: Taking Speculative Load Hardening to the Next Level · USENIX Security Symposium 2023 Spectre Declassified: Reading from the Right Place at the Wrong Time · SP 2023 |
Hardware security and side channels › microarchitectural attacks
cache attacks |
1.5 | 2 | 2025 | Slice+Slice Baby: Generating Last-Level Cache Eviction Sets in the Blink of an Eye · SP 2025 The Gates of Time: Improving Cache Attacks with Transient Execution · USENIX Security Symposium 2023 |
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre |
1.5 | 2 | 2025 | Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants) · ASPLOS (2) 2025 Spectre Declassified: Reading from the Right Place at the Wrong Time · SP 2023 |
Hardware security and side channels
cache side channel |
1.0 | 1 | 2026 | Fish and Chips: On the Root Causes of Co-Located Website-Fingerprinting Attacks · IEEE Trans. Dependable Secur. Comput. 2026 |
Network security › traffic analysis
website fingerprinting |
1.0 | 1 | 2026 | Fish and Chips: On the Root Causes of Co-Located Website-Fingerprinting Attacks · IEEE Trans. Dependable Secur. Comput. 2026 |
Processor architecture and microarchitecture › hardware-assisted security
secure processor architecture |
1.0 | 1 | 2026 | Fish and Chips: On the Root Causes of Co-Located Website-Fingerprinting Attacks · IEEE Trans. Dependable Secur. Comput. 2026 |
Cryptographic primitives and cryptanalysis › cryptographic implementation
constant-time implementation |
0.9 | 1 | 2025 | Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants) · ASPLOS (2) 2025 |
Cryptographic primitives and cryptanalysis
cryptographic implementation |
0.8 | 1 | 2024 | Testing Side-channel Security of Cryptographic Implementations against Future Microarchitectures · CCS 2024 |
Privacy and data protection
differential privacy |
0.8 | 1 | 2024 | Elephants Do Not Forget: Differential Privacy with State Continuity for Privacy Budget · CCS 2024 |
Privacy and data protection › differential privacy › privacy accounting
privacy budget |
0.8 | 1 | 2024 | Elephants Do Not Forget: Differential Privacy with State Continuity for Privacy Budget · CCS 2024 |
Hardware security and side channels › trusted execution environments
state continuity |
0.8 | 1 | 2024 | Elephants Do Not Forget: Differential Privacy with State Continuity for Privacy Budget · CCS 2024 |
Cryptographic primitives and cryptanalysis
finite field arithmetic |
0.7 | 2 | 2023 | CryptOpt: Verified Compilation with Randomized Program Search for Cryptographic Primitives · Proc. ACM Program. Lang. 2023 Curve41417: Karatsuba Revisited · CHES 2014 |
Systems and software security › information flow control
declassification |
0.7 | 1 | 2023 | Spectre Declassified: Reading from the Right Place at the Wrong Time · SP 2023 |
Systems and software security
information flow control |
0.7 | 1 | 2023 | Spectre Declassified: Reading from the Right Place at the Wrong Time · SP 2023 |
Hardware security and side channels › microarchitectural attacks
transient execution attack |
0.7 | 1 | 2023 | The Gates of Time: Improving Cache Attacks with Transient Execution · USENIX Security Symposium 2023 |
Compilers and program optimization
verified compilation |
0.7 | 1 | 2023 | CryptOpt: Verified Compilation with Randomized Program Search for Cryptographic Primitives · Proc. ACM Program. Lang. 2023 |
Processor architecture and microarchitecture
microarchitectural security |
0.7 | 1 | 2023 | BunnyHop: Exploiting the Instruction Prefetcher · USENIX Security Symposium 2023 |
Cryptographic primitives and cryptanalysis › public-key cryptography
elliptic curve cryptography |
0.4 | 2 | 2014 | Curve41417: Karatsuba Revisited · CHES 2014 Kummer Strikes Back: New DH Speed Records · ASIACRYPT (1) 2014 |
Compilers and program optimization › program transformation
compiler transformations |
0.3 | 1 | 2025 | Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants) · ASPLOS (2) 2025 |
Programming languages and type systems › type systems
type soundness |
0.3 | 1 | 2025 | Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants) · ASPLOS (2) 2025 |
Memory systems
cache design |
0.3 | 1 | 2025 | Slice+Slice Baby: Generating Last-Level Cache Eviction Sets in the Blink of an Eye · SP 2025 |
Hardware security and side channels
trusted execution environments |
0.2 | 1 | 2024 | Elephants Do Not Forget: Differential Privacy with State Continuity for Privacy Budget · CCS 2024 |
Processor architecture and microarchitecture
microarchitecture optimization |
0.2 | 1 | 2024 | Testing Side-channel Security of Cryptographic Implementations against Future Microarchitectures · CCS 2024 |
Programming languages and type systems › type systems › security type systems
information-flow type systems |
0.2 | 1 | 2023 | Spectre Declassified: Reading from the Right Place at the Wrong Time · SP 2023 |
Program verification › formal proof
mechanized proof |
0.2 | 1 | 2023 | CryptOpt: Verified Compilation with Randomized Program Search for Cryptographic Primitives · Proc. ACM Program. Lang. 2023 |
Processor architecture and microarchitecture
speculative execution |
0.2 | 1 | 2023 | Ultimate SLH: Taking Speculative Load Hardening to the Next Level · USENIX Security Symposium 2023 |
Processor architecture and microarchitecture › speculative execution
transient execution |
0.2 | 1 | 2023 | The Gates of Time: Improving Cache Attacks with Transient Execution · USENIX Security Symposium 2023 |
Cryptographic protocols and secure computation › key exchange
diffie-hellman key exchange |
0.2 | 1 | 2014 | Kummer Strikes Back: New DH Speed Records · ASIACRYPT (1) 2014 |
Methods — techniques the papers use, named apart from their topics
timing analysis · 2.0correlation analysis · 2.0value-dependent information-flow type system · 1.7microarchitectural races · 1.7hash function reversal · 1.7coq proof assistant · 1.7compiler transformation · 1.7side-channel testing · 1.5microarchitectural analysis · 1.5state continuity protocol · 0.8symbolic execution · 0.7side-channel analysis · 0.7selective speculative load hardening · 0.7randomized program search · 0.7formal verification · 0.7SMT solving · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | TimeGaps Channels: Exploiting CPU Halted Time for Fun and ProfitabstractWhat do computers do when they do not compute? To answer this question, we investigate TimeGaps, periods during program execution, in which the timestamp counter progresses while the CPU is halted. We develop techniques for identifying TimeGaps and find that on Intel processors, TimeGaps amount to over 1% of the elapsed time. We further find that TimeGaps occurrence correlate with frequency transitions at either the CPU or at the Integrated Graphics Processing Unit (iGPU). We then turn our attention to the security impact of TimeGaps under two settings: default Dynamic Voltage and Frequency Scaling (DVFS) configuration, and fixed-frequency countermeasures. Under default DVFS settings, TimeGaps exhibit leakage capabilities comparable to state-of-the-art CPU-frequency-based side channels, i.e., Hertzbleed. Leveraging this, we infer website visits with an accuracy of 98.0% on Chrome and 85.2% on Tor, and extract cryptographic keys from Cloudflare's CIRCL library. Under fixed CPU frequency, where Hertzbleed is no longer effective, TimeGaps induced by iGPU frequency transitions continue to leak iGPU instruction and operand-level information. Moreover, TimeGaps re-enable three frequency-based sidechannel attacks previously believed to be mitigated by fixing CPU frequency, including pixel stealing with a high accuracy of 98.2%, robust website fingerprinting (92.2% on Chrome, 87.4% on Tor), and keystroke detection with a precision of over 84.6%. Yusi Feng, Xin Zhang 0110, Sioli O'Connell, Liangwei Qiu, Chitchanok Chuengsatiansup, Daniel Genkin, Yuval Yarom, Yinqian Zhang, Zhi Zhang 0001 |
ISCA | 5 |
| 2026 | Fish and Chips: On the Root Causes of Co-Located Website-Fingerprinting AttacksabstractMicroarchitectural website-fingerprinting attacks use timing information to leak the browsing habits of a victim to co-resident attackers. Microarchitectural leakage in these attacks often comprises multiple sources. While most published attacks claim to identify the cause of leakage, these claims are not always well supported. Thus, so far the question of how to determine what leaks remains mostly unanswered. In this work, we develop a framework for identifying and measuring the contribution of leakage sources to the overall observations the attacker makes. Experimenting with three website-fingerprinting attacks in the literature, we qualitatively identify four main classes of leakage sources: core contention, interrupts, frequency scaling, and cache eviction. We demonstrate cases where we can completely mitigate leakage by controlling these sources. We then show that enabling each of the sources individually leaks enough to allow website-fingerprinting attacks. In the quantitative analysis, we use the correlation between events related to each source and the measured timing in the attacks as a metric to determine the relative contribution of each source to the specific attack. Our work provides insights into the leakage sources of coarse-grained microarchitectural attacks, aiding the design of secure processor systems as well as more effective attacks and defenses. Yusi Feng, Sioli O'Connell, Xin Zhang 0110, Chitchanok Chuengsatiansup, Daniel Genkin, Yuval Yarom, Yinqian Zhang, Zhi Zhang 0001 |
IEEE Trans. Dependable Secur. Comput. | 4 |
| 2025 | Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants)abstractSpectre attacks void the guarantees of constant-time cryptographic code by leaking secrets during speculative execution. Recent research shows that such code can be protected from Spectre-v1 attacks with minimal overhead, but leaves open the question of protecting against other Spectre variants. In this work, we design, validate, implement, and verify a new approach to protect cryptographic code against all known classes of Spectre attacks, in particular Spectre-RSB. Our approach combines a new value-dependent information-flow type system that ensures that no secrets leak even under speculative execution and a compiler transformation that enables it on the generated low-level code. We first prove the soundness of the type system and the correctness of the compiler transformation using the Coq proof assistant. We then implement our approach in the Jasmin framework for high-assurance cryptography and demonstrate that the overhead incurred by all Spectre protections is below 2% for most cryptographic primitives and reaches only about 5--7% for the more complex post-quantum key-encapsulationkmechanism Kyber. Santiago Arranz-Olmos, Gilles Barthe, Chitchanok Chuengsatiansup, Benjamin Grégoire, Vincent Laporte, Tiago Oliveira 0004, Peter Schwabe, Yuval Yarom, Zhiyuan Zhang 0005 |
ASPLOS (2) | 3 |
| 2025 | Slice+Slice Baby: Generating Last-Level Cache Eviction Sets in the Blink of an EyeabstractAn essential step for mounting cache attacks is finding eviction sets, collections of memory locations that contend on cache space. On Intel processors, one of the main challenges for identifying contending addresses is the sliced cache design, where the processor hashes the physical address to determine where in the cache a memory location is stored. While past works have demonstrated that the hash function can be reversed, they also showed that it depends on physical address bits that the adversary does not know. In this work, we make three main contributions to the art of finding eviction sets. We first exploit microarchitectural races to compare memory access times and identify the cache slice to which an address maps. We then use the known hash function to both reduce the error rate in our slice identification method and to reduce the work by extrapolating slice mappings to untested memory addresses. Finally, we show how to propagate information on eviction sets across different page offsets for the hitherto unexplored case of non-linear hash functions. Our contributions allow for entire LLC eviction set generation in 0.7 seconds on the Intel i7-9850H and 1.6 seconds on the i9-10900K, both using non-linear functions. This represents a significant improvement compared to state-of-the-art techniques taking 9× and 10× longer, respectively. Bradley Morgan, Gal Horowitz, Sioli O'Connell, Stephan van Schaik, Chitchanok Chuengsatiansup, Daniel Genkin, Olaf Maennel, Paul Montague, Eyal Ronen, Yuval Yarom |
SP | 5 |
| 2024 | SoK: Can We Really Detect Cache Side-Channel Attacks by Monitoring Performance Counters?abstractSharing microarchitectural components between co-resident programs leads to potential information leaks, with devastating implications on security. Over the last decade, multiple proposals suggested monitoring hardware performance counters as a method for detecting such attacks. William Kosasih, Yusi Feng, Chitchanok Chuengsatiansup, Yuval Yarom |
AsiaCCS | 3 |
| 2024 | Testing Side-channel Security of Cryptographic Implementations against Future MicroarchitecturesabstractHow will future microarchitectures impact the security of existing cryptographic implementations? As we cannot keep reducing the size of transistors, chip vendors have started developing new microarchitectural optimizations to speed up computation. A recent study (Sanchez Vicarte et al., ISCA 2021) suggests that these optimizations might open the Pandora's box of microarchitectural attacks. However, there is little guidance on how to evaluate the security impact of future optimization proposals. Gilles Barthe, Marcel Böhme, Sunjay Cauligi, Chitchanok Chuengsatiansup, Daniel Genkin, Marco Guarnieri, David Mateos Romero, Peter Schwabe, Yuval Yarom |
CCS | 4 |
| 2024 | Elephants Do Not Forget: Differential Privacy with State Continuity for Privacy BudgetabstractCurrent implementations of differentially-private (DP) systems either lack support to track the global privacy budget consumed on a dataset, or fail to faithfully maintain the state continuity of this budget. We show that failure to maintain a privacy budget enables an adversary to mount replay, rollback and fork attacks --- obtaining answers to many more queries than what a secure system would allow. As a result the attacker can reconstruct secret data that DP aims to protect --- even if DP code runs in a Trusted Execution Environment (TEE). We propose ElephantDP, a system that aims to provide the same guarantees as a trusted curator in the global DP model would, albeit set in an untrusted environment. Our system relies on a state continuity module to provide protection for the privacy budget and a TEE to faithfully execute DP code and update the budget. To provide security, our protocol makes several design choices including the content of the persistent state and the order between budget updates and query answers. We prove that ElephantDP provides liveness (i.e., the protocol can restart from a correct state and respond to queries as long as the budget is not exceeded) and DP confidentiality (i.e., an attacker learns about a dataset as much as it would from interacting with a trusted curator). Our implementation and evaluation of the protocol use Intel SGX as a TEE to run the DP code and a network of TEEs to maintain state continuity. Compared to an insecure baseline, we observe 1.1--3.2× overheads and lower relative overheads for complex DP queries. Jiankai Jin, Chitchanok Chuengsatiansup, Toby C. Murray, Benjamin I. P. Rubinstein, Yuval Yarom, Olga Ohrimenko |
CCS | 2 |
| 2023 | Spectre Declassified: Reading from the Right Place at the Wrong TimeabstractPractical information-flow programming languages commonly allow controlled leakage via a declassify construct—programmers can use this construct to declare intentional leakage. For instance, cryptographic signatures and ciphertexts, which are computed from private keys, are viewed as secret by information-flow analyses. Cryptographic libraries can use declassify to make this data public, as it is no longer sensitive.In this paper, we study the interaction between speculative execution and declassification. We show that speculative execution leads to unintended leakage from declassification sites. Concretely, we present a PoC that recovers keys from AES implementations. Our PoC is an instance of a Spectre attack, and remains effective even when programs are compiled with speculative load hardening (SLH), a widespread compiler-based countermeasure against Spectre. We develop formal countermeasures against these attacks, including a significant improvement to SLH we term selective speculative load hardening (selSLH). These countermeasures soundly enforce relative non-interference (RNI): Informally, the speculative leakage of a protected program is limited to the existing sequential leakage of the original program. We implement our simplest countermeasure in the FaCT language and compiler—which is designed specifically for high-assurance cryptography—and we see performance overheads of at most 10%. Finally, although we do not directly implement selSLH, our preliminary evaluation suggests a significant reduction in performance cost for cryptographic functions as compared to traditional SLH. Basavesh Ammanaghatta Shivakumar, Jack Barnes, Gilles Barthe, Sunjay Cauligi, Chitchanok Chuengsatiansup, Daniel Genkin, Sioli O'Connell, Peter Schwabe, Rui Qi Sim, Yuval Yarom |
SP | 5 |
| 2023 | The Gates of Time: Improving Cache Attacks with Transient Execution
Daniel Katzman, William Kosasih, Chitchanok Chuengsatiansup, Eyal Ronen, Yuval Yarom |
USENIX Security Symposium | 3 |
| 2023 | Ultimate SLH: Taking Speculative Load Hardening to the Next Level
Zhiyuan Zhang 0005, Gilles Barthe, Chitchanok Chuengsatiansup, Peter Schwabe, Yuval Yarom |
USENIX Security Symposium | 3 |
| 2023 | BunnyHop: Exploiting the Instruction Prefetcher
Zhiyuan Zhang 0005, Mingtian Tao, Sioli O'Connell, Chitchanok Chuengsatiansup, Daniel Genkin, Yuval Yarom |
USENIX Security Symposium | 4 |
| 2023 | Row, Row, Row Your Boat: How to Not Find Weak Keys in PilsungabstractAbstract The Pilsung cipher is part of the North Korean Red Star operating system, which was leaked to the West in 2014. Initial analysis by Kryptos Logic reported a possibility of a class of weak keys due to the use of pseudo-random diffusion. Following this lead, we analyzed the cipher and identified a small class of such weak keys. We developed techniques for searching for a key that belongs to the class. After spending thousands of CPU hours, we found a supposedly weak key for a slightly weaker version of Pilsung, but the key did not behave as we expected. On further investigation we found out a crucial misunderstanding in a critical part of the cipher and that no such class of weak keys exists in Pilsung. Thus, this paper makes two main contributions to the art of cryptanalysis. First, it identifies and shows how to investigate a potential weakness in randomizing diffusion, which although does not exist in Pilsung, may affect future designs. Second, it highlights the need for early verification of results in order to identify errors before expending significant resources. Chitchanok Chuengsatiansup, Eyal Ronen, Gregory G. Rose, Yuval Yarom |
Comput. J. | 1 |
| 2023 | CryptOpt: Verified Compilation with Randomized Program Search for Cryptographic PrimitivesabstractMost software domains rely on compilers to translate high-level code to multiple different machine languages, with performance not too much worse than what developers would have the patience to write directly in assembly language. However, cryptography has been an exception, where many performance-critical routines have been written directly in assembly (sometimes through metaprogramming layers). Some past work has shown how to do formal verification of that assembly, and other work has shown how to generate C code automatically along with formal proof, but with consequent performance penalties vs. the best- known assembly. We present CryptOpt, the first compilation pipeline that specializes high-level cryptographic functional programs into assembly code significantly faster than what GCC or Clang produce, with mechanized proof (in Coq) whose final theorem statement mentions little beyond the input functional program and the operational semantics of x86-64 assembly. On the optimization side, we apply randomized search through the space of assembly programs, with repeated automatic benchmarking on target CPUs. On the formal-verification side, we connect to the Fiat Cryptography framework (which translates functional programs into C-like IR code) and extend it with a new formally verified program-equivalence checker, incorporating a modest subset of known features of SMT solvers and symbolic-execution engines. The overall prototype is quite practical, e.g. producing new fastest-known implementations of finite-field arithmetic for both Curve25519 (part of the TLS standard) and the Bitcoin elliptic curve secp256k1 for the Intel 12𝑡ℎ and 13𝑡ℎ generations. Joel Kuepper, Andres Erbsen, Jason Gross, Owen Conoly, Chuyue Sun, Samuel Tian, Adam Chlipala, Chitchanok Chuengsatiansup, Daniel Genkin, Markus Wagner 0007, Yuval Yarom |
Proc. ACM Program. Lang. | 9 |
| 2022 | RSA Key Recovery from Digit Equivalence Information
Chitchanok Chuengsatiansup, Andrew Feutrill, Rui Qi Sim, Yuval Yarom |
ACNS | 1 |
| 2022 | Side-Channeling the Kalyna Key Expansion
Chitchanok Chuengsatiansup, Daniel Genkin, Yuval Yarom, Zhiyuan Zhang 0005 |
CT-RSA | 1 |
| 2020 | ModFalcon: Compact Signatures Based On Module-NTRU LatticesabstractLattices lead to promising practical post-quantum digital signatures, combining asymptotic efficiency with strong theoretical security guarantees. However, tuning their parameters into practical instantiations is a delicate task. On the one hand, NIST round~2 candidates based on Lyubashevsky's design (such as dilithium and qtesla) allow several tradeoffs between security and efficiency, but at the expense of a large bandwidth consumption. On the other hand, the hash-and-sign falcon signature is much more compact and is still very efficient, but it allows only two security levels, with large compactness and security gaps between them. We introduce a new family of signature schemes based on the falcon design, which relies on module lattices. Our concrete instantiation enjoys the compactness and efficiency of falcon, and allows an intermediate security level. It leads to the most compact lattice-based signature achieving a quantum security above 128 bits. Chitchanok Chuengsatiansup, Thomas Prest, Damien Stehlé, Alexandre Wallet, Keita Xagawa |
AsiaCCS | 1 |
| 2019 | Towards Practical GGM-Based PRF from (Module-)Learning-with-Rounding
Chitchanok Chuengsatiansup, Damien Stehlé |
SAC | 1 |
| 2017 | NTRU Prime: Reducing Attack Surface at Low Cost
Daniel J. Bernstein, Chitchanok Chuengsatiansup, Tanja Lange 0001, Christine van Vredendaal |
SAC | 2 |
| 2014 | Kummer Strikes Back: New DH Speed Records
Daniel J. Bernstein, Chitchanok Chuengsatiansup, Tanja Lange 0001, Peter Schwabe |
ASIACRYPT (1) | 2 |
| 2014 | Curve41417: Karatsuba Revisited
Daniel J. Bernstein, Chitchanok Chuengsatiansup, Tanja Lange 0001 |
CHES | 2 |
| 2013 | PandA: Pairings and Arithmetic
Chitchanok Chuengsatiansup, Michael Naehrig, Pance Ribarski, Peter Schwabe |
Pairing | 1 |
| 2012 | Faster elliptic curve arithmetic for double-base chain by reordering sequences of field operations
Chitchanok Chuengsatiansup |
ISITA | 1 |