Field-programmable gate array (FPGA) is a preferred solution for a CMOS image sensor (CIS) automatic test equipment (ATE) because it provides fast upgradability for the timely testing of CIS products using a new interface protocol. However, implementing a Mobile Industry Processor Interface (MIPI) C-PHY receiver to receive images from the CIS in an FPGA can be challenging due to the use of three wires, three distinct voltage levels, and the requirements of fast clock data recovery (CDR) lock time and wide CDR tracking bandwidth. To overcome these challenges, we have developed an FPGA-only MIPI C-PHY receiver that utilizes a blind oversampling CDR technique, which offers fast CDR lock time and wide CDR bandwidth. We used an Altera Stratix 10 GX FPGA as an oversampling device by operating its transceiver in a lock-to-reference-clock mode. We developed a parallel gate-based clock recovery algorithm and a fork and join-based data decision algorithm. As a result, we were able to test CIS wafers at symbol rates of up to 3.5 Giga-symbols per second, achieving performance comparable to that of sophisticated ASIC-based CIS ATEs.