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Yohei Ishikawa

dblp:125/2551 · DBLP profile ↗
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3ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0003-3888-035XORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 since 2021Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Audio and music processing · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Audio and music processing › microphone array processing
adaptive beamforming
0.112011
Musical Noise Controllable Algorithm of Channelwise Spectral Subtraction and Adaptive Beamforming Based on Higher Order Statistics · IEEE Trans. Speech Audio Process. 2011
Audio and music processing
microphone array processing
0.112011
Musical Noise Controllable Algorithm of Channelwise Spectral Subtraction and Adaptive Beamforming Based on Higher Order Statistics · IEEE Trans. Speech Audio Process. 2011
Audio and music processing › acoustic signal processing › audio signal reconstruction › audio restoration
musical noise suppression
0.112011
Musical Noise Controllable Algorithm of Channelwise Spectral Subtraction and Adaptive Beamforming Based on Higher Order Statistics · IEEE Trans. Speech Audio Process. 2011
Audio and music processing › speech enhancement
noise reduction
0.112011
Musical Noise Controllable Algorithm of Channelwise Spectral Subtraction and Adaptive Beamforming Based on Higher Order Statistics · IEEE Trans. Speech Audio Process. 2011

Methods — techniques the papers use, named apart from their topics

higher-order statistics · 0.1channelwise spectral subtraction · 0.1
YearPublicationVenuePosition
2024 HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL
abstract
HDLRuby is a new hardware description language defined as an extension of the Ruby programming language aiming to improve circuit design productivity. HDLRuby allows to model digital circuits at the register transfer level while supporting high-level paradigms comprising object-oriented programming, genericity, metaprogramming, and reflection. By construction, HDLRuby can also execute any code in Ruby and supports all of its libraries. Yet, even if high-level features are beneficial for design productivity, such advantages can be negated if the design tools are not efficient enough for producing in reasonable time quality hardware. This article investigates this issue by presenting the techniques used for compiling HDLRuby descriptions and by evaluating their performance. In detail, it explains how the language has been implemented and how it is translated to synthesizable Verilog HDL. Experiments are then presented for confirming the productivity gain of using HDLRuby and for evaluating the performance of the translation, the size of the resulting code, and the time required by a commercially available synthesis tool to produce an FPGA configuration from it. The HDLRuby descriptions used for the experiments include a set of repetitive designs for single construct evaluations and the implementation of generic convolution neural networks for real-life applications. For these evaluations, the translation time proves to be more than 10 times shorter than the synthesis time.
Lovic Gauthier, Yohei Ishikawa
ACM Trans. Embed. Comput. Syst.2
2019 Headphone Amplifier and its Layout for Education for High School Student
abstract
This paper presents a headphone amplifier and its layout for a novel education about analog CMOS for high school students. Some circuit blocks are prepared so that the high school students can design an analog CMOS circuit. The students can design a headphone amplifier by connecting the respective circuit blocks. Even when laying out, the students need only connecting the prepared layout blocks. Special layout blocks that the students can be easily laid out are prepared. The proposed circuit blocks are simulated by HSPICE using 0.6 μm CMOS parameters.
Chiharu Umezaki, Takashi Yoshitomi, Yohei Ishikawa, Akio Shimizu, Takuro Noguchi, Sumio Fukai
ISCAS3
2011 Musical Noise Controllable Algorithm of Channelwise Spectral Subtraction and Adaptive Beamforming Based on Higher Order Statistics
abstract
In this paper, we propose a musical-noise-controllable algorithm for array signal processing with the aim for high-performance and high-quality noise reduction. Recently, many methods of integrating linear microphone array signal processing and nonlinear signal processing for noise reduction have been studied, but these methods often suffer from the problem of musical noise. In the proposed algorithm, channelwise spectral subtraction is applied before adaptive array signal processing. We also introduce a new automatic control algorithm to obtain the subtraction strength parameter used in the spectral subtraction, which depends on the amount of generated musical noise, measured by higher order statistics. We confirm the effectiveness of the proposed algorithm via objective and subjective evaluations.
Hiroshi Saruwatari, Yohei Ishikawa, Yu Takahashi, Takayuki Inoue, Kiyohiro Shikano, Kazunobu Kondo
IEEE Trans. Speech Audio Process.2