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Wolfgang Wieser

dblp:125/7512 · DBLP profile ↗
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6ranked-venue papers
1as first author
0since 2021 · last 2020
0000-0003-0891-1418ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 3Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
2 papers
Cryptographic primitives and cryptanalysis · 75% Authentication and access control · 25%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Computer networks
1 paper
Internet of things and sensor networks · 100%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis
authenticated encryption
0.212015
NaCl's Crypto_box in Hardware · CHES 2015
Cryptographic primitives and cryptanalysis › public-key cryptography › public-key encryption
public-key authenticated encryption
0.212015
NaCl's Crypto_box in Hardware · CHES 2015
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.212015
NaCl's Crypto_box in Hardware · CHES 2015
Hardware accelerators and domain-specific architectures › cryptographic accelerator
elliptic curve cryptography hardware
0.212015
NaCl's Crypto_box in Hardware · CHES 2015
Authentication and access control › access control
physical access control
0.212013
Security analysis of a widely deployed locking system · CCS 2013
Internet of things and sensor networks › resource-constrained devices
resource-constrained iot devices
0.112015
NaCl's Crypto_box in Hardware · CHES 2015

Methods — techniques the papers use, named apart from their topics

security analysis · 0.2
YearPublicationVenuePosition
2020 Simultaneous Morphological and Flow Imaging Enabled by Megahertz Intravascular Doppler Optical Coherence Tomography
abstract
We demonstrate three-dimensional intravascular flow imaging compatible with routine clinical image acquisition workflow by means of megahertz (MHz) intravascular Doppler Optical Coherence Tomography (OCT). The OCT system relies on a 1.1 mm diameter motorized imaging catheter and a 1.5 MHz Fourier Domain Mode Locked (FDML) laser. Using a post processing method to compensate the drift of the FDML laser output, we can resolve the Doppler phase shift between two adjoining OCT A-line datasets. By interpretation of the velocity field as measured around the zero phase shift, the flow direction at specific angles can be qualitatively estimated. Imaging experiments were carried out in phantoms, micro channels, and swine coronary artery in vitro at a speed of 600 frames/s. The MHz wavelength sweep rate of the OCT system allows us to directly investigate flow velocity of up to 37.5 cm/s while computationally expensive phase-unwrapping has to be applied to measure such high speed using conventional OCT system. The MHz sweep rate also enables a volumetric Doppler imaging even with a fast pullback at 40 mm/s. We present the first simultaneously recorded 3D morphological images and Doppler flow profiles. Flow pattern estimation and three-dimensional structural reconstruction of entire coronary artery are achieved using a single OCT pullback dataset.
Tianshi Wang 0003, Tom Pfeiffer, Joost Daemen, Frits Mastik, Wolfgang Wieser, Anton F. W. van der Steen, Gijs van Soest
IEEE Trans. Medical Imaging5
2019 A Calibratable Detector for Invasive Attacks
abstract
Microprobing is commonly used by adversaries to extract firmware or cryptographic keys from microcontrollers. We introduce the calibratable lightweight invasive attack detector (CaLIAD) to detect microprobing attacks. The CaLIAD measures timing imbalances between lines that are caused by the capacitive load of a probe. Compared to protection mechanisms from industry, it does not require an additional protection layer such as meshes do; in contrast to bus encryption, it does not introduce delay cycles. Compared to state-of-the-art low area probing detectors, it can be calibrated and, thus, allows compensating manufacturing variations as well as small layout imbalances. This capability allows us to significantly reduce the detection margin compared to the prior art while maintaining the low rate of false positives. We can finally show that capacitive loads of 23 fF or less can be detected, depending on how the CaLIAD is used. This includes all state-of-the-art commercial microprobes we are aware of.
Michael Weiner 0004, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich
IEEE Trans. Very Large Scale Integr. Syst.2
2015 NaCl's Crypto_box in Hardware
abstract
This paper presents a low-resource hardware implementation of the widely used crypto_box function of the Networking and Cryptography library (NaCl). It supports the X25519 Diffie-Hellman key exchange using Curve25519, the Salsa20 stream cipher, and the Poly1305 message authenticator. Our targeted application is a secure communication between devices in the Internet of Things (IoT) and Internet servers. Such devices are highly resource-constrained and require carefully optimized hardware implementations. We propose the first solution that enables 128-bit-secure public-key authenticated encryption on passively-powered IoT devices like WISP nodes. From a cryptographic point of view we thus make a first step to turn these devices into fully-fledged participants of Internet communication. Our crypto processor needs a silicon area of 14.6 kGEs and less than 40 $$\mu $$ W of power at 1 MHz for a 130 nm low-leakage CMOS process technology.
Michael Hutter, Jürgen Schilling, Peter Schwabe, Wolfgang Wieser
CHES4
2014 Efficient Multiplication on Low-Resource Devices
abstract
In this paper, we evaluate various large-integer multiplication methods suitable for resource-constrained devices like passive RFIDs. We restrict our investigations on multi-precision multiplication units in hardware and evaluate their performance regarding area, power, and speed. We implemented and compared different multiplier techniques: array, bit-and digit-serial, Booth, and Karatsuba. We synthesized all designs for a 130 nm low-leakage CMOS process technology. In total, we compared 21 different multipliers with input-word sizes ranging from 8 to 64 bits and having an operating frequency of 1 MHz. The best area-time-power product has been achieved by a 4-bit digit-serial multiplication method. These results are interesting because they have been fairly obtained from a single design flow and by using the same tools. The results can serve as first estimation criterias for forecasting the costs for multiplication-demanding applications running on devices with very limited resources.
Wolfgang Wieser, Michael Hutter
DSD1
2013 Security analysis of a widely deployed locking system
abstract
Electronic locking systems are rather new products in the physical access control market. In contrast to mechanical locking systems, they provide several convenient features such as more flexible access rights management, the possibility to revoke physical keys and the claim that electronic keys cannot be cloned as easily as their mechanical counterparts. While for some electronic locks, mechanical flaws have been found, only a few publications analyzed the cryptographic security of electronic locking systems. In this paper, we analyzed the electronic security of an electronic locking system which is still widely deployed in the field.
Michael Weiner 0004, Maurice Massar, Erik Tews, Dennis Giese, Wolfgang Wieser
CCS5
2013 Efficient Vector Implementations of AES-Based Designs: A Case Study and New Implemenations for Grøstl
Severin Holzer-Graf, Thomas Krinninger, Martin Pernull, Martin Schläffer, Peter Schwabe, David Seywald, Wolfgang Wieser
CT-RSA7