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Andrew Love

dblp:126/3616 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 50% Electronic design automation · 25% Storage systems · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › design automation tools › FPGA CAD
FPGA design tools		 0.212013
FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only) · FPGA 2013
Reconfigurable computing and FPGAs
FPGA implementation		 0.212013
FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only) · FPGA 2013
Reconfigurable computing and FPGAs › FPGA compilation
incremental compilation		 0.212013
FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only) · FPGA 2013
Storage systems
metadata management		 0.212013
FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only) · FPGA 2013

Methods — techniques the papers use, named apart from their topics

incremental compilation · 0.2
YearPublicationVenuePosition
2013 FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only)
abstract
No abstract available.
Andrew Love, Peter M. Athanas
 FPGA1
2013 Rapid modular assembly of Xilinx FPGA designs
abstract
This paper presents an alternative FPGA design compilation flow that reduces the back-end time required to implement a design. Beginning with the GReasy front-end and proceeding through the TFlow back-end, this flow consists of a rapid method for design assembly, decoupled from the vendor tools. This enables software-like turnaround time for faster prototyping and increased productivity.
Andrew Love, Peter M. Athanas
 FPL1
2013 In pursuit of instant gratification for FPGA design
abstract
This paper describes an alternative FPGA design compilation flow to reduce the back-end time required to implement a Xilinx FPGA design. Using a library of precompiled modules and associated meta-data, bitstream-level assembly of desired designs can occur in a fraction of the time of traditional back-end tools. Modules are bound, placed, and routed using custom bitstream assembly with the primary objective of rapid compilation while preserving performance. Since vendor tools are not needed for assembly, compilation can be performed in embedded and/or untethered environments. As a result, large device compilations can be assembled in seconds. This turbo flow (TFlow) enables software-like turn-around time for faster prototyping and increased productivity.
Andrew Love, Wenwei Zha, Peter M. Athanas
 FPL1