The design of the memristor emulator, which has found widespread of applications in analog computation, neuromorphic and biological systems, communications, etc., is much sought for. In this article, a resistorless electronically tunable grounded and floating memristor emulator by employing current-mode (CM) building blocks: operational transconductance amplifier (OTA) and voltage differencing buffered amplifier (VDBA) has been proposed. The proposed emulators can be configured as incremental and decremental operations. The robustness of the proposed emulator has been verified by performing various analyses: nonideal interpretations, process corner variations, temperature fluctuations, and nonvolatility behavior. The layout has been performed, and the theoretical fingerprint characteristics have been simulated and observed using 180-nm CMOS process parameters in the Cadence environment. The pinched hysteresis loop of the proposed memristor emulator maintains up to 5 MHz. The proposed memristor emulator uses less number of circuit components, but it maintains performance in terms of speed and operating range of frequency. Binary frequency shift keying (BFSK) has been performed using the proposed memristor to validate its functionality in the application. This memristor emulator with superior performance can be integrated into the communication system, analog computation, neuromorphic and biological systems, etc.

Three novel configurations of second order inverse band reject filters (IBRFs) are proposed in this work by using a single operational transresistance amplifier (OTRA). The working of the proposed inverse filters are verified in simulation by implementing 180 nm CMOS model of OTRA in SPICE and also in hardware with AD844AN IC. Theoretical frequency response characteristics of all the three proposed configurations match very well with the simulated characteristics. Layout of the proposed configuration has been implemented using Analog Design Environment (ADE) tool of cadence virtuoso to study the feasibility of operation. Monte Carlo analysis has also been performed to study the effect of variation in passive components on the performance of the circuits. Sensitivity analysis has been studied.

Increasing demand of high-speed portable modules for multimedia applications has motivated the development of hardware-based solutions for image processing applications. Most of the nonrigid image registration algorithms are found to be unsuitable for hardware implementation because of their nonlinearity and computationally intensive nature. In this paper, an algorithm for nonrigid image registration based on Demons approximation is proposed. The algorithm has been simulated in MATLAB and results show a 15% improvement in peak-signal-to-noise-ratio with a 17% reduction in registration time for 256 × 256 image over the original Demons algorithm. The proposed algorithm is synthesized in Virtex6-xc6vlx760-2-ff1760 and maximum synthesized frequency is found to be 174 MHz. The proposed architecture provides the low cost, high-speed solution for the registration process, which is also helpful for making a portable system.

No rigid registration helps to recover local warping which occurs during image acquisition. The speed of operation is one of the bottlenecks in nonrigid registration which is addressed by only a few. In the present paper an efficient Demons approach is presented which not only increases the speed of the registration task, but also retains the performance of algorithm.

Motion estimation is an important task in the video encoding process. This plays an important role for high definition television (HDTV) and internet broadcasting as well as in medical imaging system like dynamic MRI. Accurate estimation of the predicted frame is required in dynamic MRI. The block search method is very easy to implement, but it estimates very poorly if complex motion is present in the frame sequences. In this paper, we present a new affine based motion estimation method which can be used for medical video processing. The proposed method provides sufficient parallelism in the implementation while giving good result in terms of motion estimation.