Demo Data from SIGIR 2026 / reviewers in the wild / expert
Naiyong Jin
dblp:13/5521
· DBLP profile ↗
13ranked-venue papers
5as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 11 · 5 first-authorTheory of computation · 5
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
3 papers |
Automated reasoning and model checking · 46% Logic in computer science · 39% Automata and formal languages · 14% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Logic in computer science
temporal logic |
0.2 | 1 | 2013 | SVA and PSL Local Variables - A Practical Approach · CAV 2013 |
Automated reasoning and model checking › synthesis › temporal logic synthesis
LTL synthesis |
0.1 | 1 | 2012 | Acacia+, a Tool for LTL Synthesis · CAV 2012 |
Automata and formal languages
automata algorithms |
0.1 | 1 | 2009 | An Antichain Algorithm for LTL Realizability · CAV 2009 |
Logic in computer science › temporal logic
linear temporal logic |
0.1 | 1 | 2009 | An Antichain Algorithm for LTL Realizability · CAV 2009 |
Methods — techniques the papers use, named apart from their topics
assertion checking · 0.2automata construction · 0.1antichain algorithm · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | SVA and PSL Local Variables - A Practical Approach
Roy Armoni, Dana Fisman, Naiyong Jin |
CAV | 3 |
| 2013 | Exploiting structure in LTL synthesis
Emmanuel Filiot, Naiyong Jin, Jean-François Raskin |
Int. J. Softw. Tools Technol. Transf. | 2 |
| 2012 | Acacia+, a Tool for LTL Synthesis
Aaron Bohy, Véronique Bruyère, Emmanuel Filiot, Naiyong Jin, Jean-François Raskin |
CAV | 4 |
| 2011 | Antichains and compositional algorithms for LTL synthesis
Emmanuel Filiot, Naiyong Jin, Jean-François Raskin |
Formal Methods Syst. Des. | 2 |
| 2010 | Compositional Algorithms for LTL Synthesis
Emmanuel Filiot, Naiyong Jin, Jean-François Raskin |
ATVA | 2 |
| 2009 | An Antichain Algorithm for LTL Realizability
Emmanuel Filiot, Naiyong Jin, Jean-François Raskin |
CAV | 2 |
| 2008 | iPSL: An Environment for IP-Based PSL SpecificationabstractIn PSL, behavioral properties of an IP core and its environment are directed by different directives. Improperly directed properties will severely impact the validity of refinement verification, specification assurance, and the evolution of specification hierarchy. In this paper, we introduce a tool iPSL which supports users to apply IP-based design methodology to PSL specifications. iPSL incorporates three methods for principled construction of PSL specifications. 1) We propose rules which restrict operand types of temporal operators so that we can check whether properties are correctly directed in expressing their roles. 2) We propose semantics for composing IP-based PSL specification. With the semantics, we can pick out properties which need further abstractions after composition. 3) We also provide a semantics for the inherit operator so that we can evolve a system specification from those of existing IP cores. Naiyong Jin, Taoyong Ni |
ICECCS | 1 |
| 2008 | ASERE: Assuring the Satisfiability of Sequential Extended Regular Expressions
Naiyong Jin, Huibiao Zhu |
ISoLA | 1 |
| 2007 | Dynamic Verifying The Properties of The Simple Subset of PSLabstractPSL is a standard specification language(IEEE-1850) for hardware and embedded system design. The simple subset of PSL(PSLSimple) conforms to the notion of monotonic advancement of time, which in turn ensures that formulas within the subset can be simulated easily. Dynamic verifiers consider only finite executions which may be too short to assure their satisfaction to some formulas. In this paper, we work on the theories and methods for designing dynamic verifiers for PSLSimple. We first study the formalism for the formula satisfaction strengths over finite words. Then, we explore the combinational laws of finite words with respect to strong satisfaction, weak satisfaction and strong violation. That contributes acceptance conditions for automata to recognize not just violating, but also strongly satisfying and pending words for all PSLsimplestructures. In the end, we propose the local-variable-enhanced alternating finite automata( LAFA) as the run time checkers for PSLSimple. The size of a LAFA is linear to the size of its PSLSimpleformula. Naiyong Jin, Chengjie Shen |
TASE | 1 |
| 2006 | An Operational Semantics of an Event-Driven System-Level SimulatorabstractAs a system-level modelling language, SystemC possesses some new and interesting features such as delayed notifications, notification cancelling, notification overriding and delta-cycle. It is challenging to formalise SystemC. In this paper, we first select a kernel subset of SystemC and study its operational semantics. Based on the operational semantics we define a bisimulation relation, from which program equivalence is explored. Finally, we present a set of algebraic laws for the subset language, which can be proved based on the operational semantics model via bisimulation Xiaoqing Peng, Huibiao Zhu, Jifeng He 0001, Naiyong Jin |
SEW | 4 |
| 2005 | Towards A Truly Concurrent Model for Processes Sharing ResourcesabstractConventional theories of concurrency reduce parallel processes to sequential ones. Here, we propose a true concurrency trace model which takes variables of parallel processes as a whole and runs parallel processes as simultaneous updates on variables. By equipping each resource an ownership variable, the model has a uniform treatment to both variable access conflicts and resource conflicts. A denotational semantics based on the model is studied. After that, we show how to use this model to build a correct resource scheduler, and specify pre-compilers such that the resulting systems do not incur conflicts and have less chance of deadlocks. Naiyong Jin, Jifeng He 0001 |
SEFM | 1 |
| 2004 | Integrating Variants of DC
Jifeng He 0001, Naiyong Jin |
ICTAC | 2 |
| 2004 | Resource Models and Pre-Compiler Specification for Hardware/Software Co-Design Language
Naiyong Jin, Jifeng He 0001 |
SEFM | 1 |