Ising machines are expected to solve combinatorial optimization problems efficiently by representing them as Ising models or equivalent quadratic unconstrained binary optimization (QUBO) models . However, upper bound exists on the computable problem size due to the hardware limitations of Ising machines. This paper propose a new hybrid annealing method based on partial QUBO extraction, called subQUBO model extraction, with multiple solution instances. For a given QUBO model, the proposed method obtains$N_I$quasi-optimal solutions (quasi-ground-state solutions) in some way using a classical computer. The solutions giving these quasi-optimal solutions are calledsolution instances. We extract a size-limited subQUBO model as follows based on a strong theoretical background: we randomly select$N_S$$(N_S

Annealing machines have been developed as non-von Neumann computers aimed at solving combinatorial optimization problems efficiently. To use annealing machines for solving combinatorial optimization problems, we have to represent the objective function and constraints by an Ising model, which is a theoretical model in statistical physics. Further, it is necessary to transform the Ising model according to the hardware limitations. In the transformation, the process of effectively reducing the bit-widths of coefficients in the Ising model has hardly been studied so far. Thus, when we consider the Ising model with a large bit-width, a naive method, which means right bit-shift, has to be applied. Since it is expected that obtaining highly accurate solutions is difficult by the naive method, it is necessary to construct a method for efficiently reducing the bit-width. This article proposes methods for reducing the bit-widths of interaction and external magnetic field coefficients in the Ising model and proves that the reduction gives theoretically the same ground state of the original Ising model. The experimental evaluations also demonstrate the effectiveness of our proposed methods.

A heuristic algorithm is one of the approaches to solve an NP-hard problem. In order to enhance the capability of the system, heterogeneous computing is often adapted. In this paper, we propose an FPGA-based heterogeneous solver for three-dimensional routing. The proposed system is implemented into multiple FPGA boards and a single-board computer. The experimental results demonstrate that the proposed system outperforms a single FPGA system.

In electric circuits, errors are ineluctable. When upper bits of binary signals flip due to noise, the value will increase or decrease drastically. On the other hand, if stochastic numbers are used, the change on their values are the same since all the bits have the same weight. Therefore, stochastic computing, a computation method based on stochastic numbers, is attracting interest. Stochastic computing does have error tolerance, but cannot restore the bit stream if the bits are erroneous. Here, this paper focuses on evaluating the error-free value from the bit error rate and the erroneous value. In this paper, we propose a method to correct errors of stochastic numbers by measuring the bit error rate and filtering the values properly. From experimental evaluations, in environment with errors of more than 21%, this proposal will give a better peak-signal-to-noise ratio compared with a conventional error correction coding.

Due to the continuous demand of small-sized circuits in the fields of image processing and artificial intelligence, stochastic computing has attracted much attention. In stochastic computing, stochastic numbers composed of randomly generated bit streams are used for computation. When inputting two or more identical values to a stochastic circuit, their arithmetic operation results can be inaccurate. In this paper, a stochastic number duplicator called RRR (Register based Re-arrangement circuit using a Random bit stream) duplicator is introduced and is evaluated by applying to composite arithmetic circuits including re-convergence paths. The stochastic numbers duplicated by RRR duplicator have the equivalent values to its input stochastic numbers but have independent bit streams, effectively utilizing bit re-arrangement based on randomized bit streams. It is applied to composite arithmetic circuits and its accuracy and area/delay requirements are evaluated. The results demonstrate that RRR duplicator obtains more accurate results in a circuit with re-convergence paths, reducing the mean square errors by 64%- 94% compared to a conventional stochastic number duplicator.

Recently, the requirement for non-volatile memory on embedded systems has increased because they can be applied with normally-off and power gating technologies to. However, they have a lower endurance than volatile memories. When data is encoded as a write-reduction code appropriately, the endurance of non-volatile memory can be enhanced by writing the encoded data into the memory. We propose a highly effective write-reduction method for a multi-level cell (MLC) non-volatile memory focusing on the write-reduction code (WRC) as the optimal bit-write reduction method. The WRC can be applied only to single-level cell non-volatile memory. The proposed method generates a cell-write reduction code based on the WRC; the cell has multiple bits as the holdable data. Our proposed method achieves a cell-write reduction by 31.6% compared to the conventional method.

Non-volatile memory has many advantages over SRAM. However, one of its largest problems is that it consumes a large amount of energy in writing. In this paper, we propose a bit-write reduction method based on error correcting codes for non-volatile memories. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. We focus on error-correcting codes and generate new codes called write-reduction codes. In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to a data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. We perform several experimental evaluations and demonstrate up to 72% energy reduction.

Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2% and also energy consumption of non-volatile memory cells by up to 27.9% compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.