Post-quantum cryptography (PQC) is becoming increasingly critical for securing Internet of Things (IoT) applications against potential threats posed by quantum computers. However, cryptographic schemes based on mathematically hard problems, such as lattice-based constructions, may face reduced security margins due to ongoing cryptanalytic advancements. In IoT use cases requiring long-term deployment without guaranteed secure updates, symmetric-based signature schemes, such as$\mathsf {SPHINCS+}$, whose security relies solely on symmetric primitives, are considered robust alternatives. Among these,$\textsf {AIMer}$, selected as a finalist in the KpqC competition, is emerging as a promising candidate. This article presents optimized software implementations of$\textsf {AIMer}$for various IoT platforms, ranging from low-end to high-end devices. We propose memory-optimized and time–memory tradeoff implementations for resource-constrained ARM Cortex-M4 devices, and single instruction multiple data (SIMD)-accelerated implementations for AArch64 and AVX2 architectures. Furthermore, we conduct a comprehensive performance evaluation comparing our optimized implementations with other PQC signature schemes. Our results show that$\textsf {AIMer}$achieves significantly smaller signature sizes and faster key generation and signing compared to$\mathsf {SPHINCS+}$across all security levels, making it a viable option for long-term IoT deployment.

Post-quantum signature schemes based on the MPC-in-the-Head (MPCitH) paradigm are recently attracting significant attention as their security solely depends on the one-wayness of the underlying primitive, providing diversity for the hardness assumption in post-quantum cryptography. Recent MPCitH-friendly ciphers have been designed using simple algebraic S-boxes operating on a large field in order to improve the performance of the resulting signature schemes. Due to their simple algebraic structures, their security against algebraic attacks should be comprehensively studied.