This paper describes a functional verification methodology for multi-standard wireless Systems-on-Chip (SoC) based on SystemC Virtual Prototyping (VP). The proposed semiautomatic pin-accurate RF VP generation method reduces huge handcrafting work to abstract circuitry into the event-driven simulation domain with satisfactory accuracy, while enabling the flexibility to choose different abstraction levels. A seamless transition between various signal abstractions is enabled by operator overload, e.g. passband and equivalent baseband in order to minimize simulation time according to test cases. This methodology is demonstrated for a low power RF transceiver with the achieved simulation speed of 500μs in 10s computation time.

Direct current measurement is one of the most important control characteristics for DC-DC converters. This sensitive method is used for current control of converters, which is much faster and more accurate than voltage control. Unfortunately, the sensitivity of the current measurement is also its major drawback. Especially in automotive applications, electromagnetic interference of the increasing number of electrical appliances severely degrade the performance of analog signal processing. Having proven to be more robust and error-prone, digital signal processing has to be preferred. This work presents a universal high-side current measurement at automotive battery voltage levels up to 24 V with direct analog-to-digital (A/D) conversion in a 180 nm technology. The A/D converter has been realized as 9 bit successive-approximation (SAR) ADC, with a sampling rate of 10 MS/s to detect DC-DC converter switching frequencies above 1 MHz. The combined circuit area of 0.2 mm2dissipated less than 2 mA at 1.8 V supply voltage. Simulation results of the extracted layout reflect the transient waveforms of a DC-DC LED driver during continuous and discontinuous conduction mode.

Photovoltaic (PV) energy harvesting suffers from output energy reduction due to shading, dirt accumulation or manufacturing variability. Typical PV modules consist of 60 solar cells connected in series. Hence, shading a single cell can cause a whole substring of 20 cells to be bypassed. To overcome these drawbacks, this paper proposes the application of boost converters on submodular level, cutting the series connection to only a few cells. System level simulations prove that this architecture features increased output energy compared to state-of-the-art approaches like power optimizers. For reducing component costs and increasing system reliability, an ASIC for this application has been developed in a 150nm CMOS technology. This paper describes the design and the implementation of a highly efficient hysteretic controlled boost converter. Its high switching frequency of more than 500 kHz enables operation on a single phase while achieving an RMS input current ripple of less than 1.5 % required in photovoltaic applications. Measurements prove a RMS current ripple of less than 1 % and a maximum switching frequnecy of 650 kHz.

Photovoltaic applications require very small current and voltage ripples at the output of the solar cells to avoid power losses due to deviations from the maximum power point. Digital control offers optimization potentials to reduce this ripple without increasing the requirements on the analog-to-digital converters or the loop delay. This paper investigates the achievable current ripple reduction for two different digital current prediction algorithms applied to a hysteretic controlled photovoltaic submodule converter. A basic method relying on the continuity of the inductor current and an advanced algorithm, which compensates loop delay have been implemented in VHDL. Both methods are compared in structure and simulation results. The basic current prediction reduces the current ripple by 11 %, whereas the advanced current prediction decreases the ripple in total by 26 %. The whole controller including the advanced current prediction requires less than 0.1mm2in a 150nm CMOS technology.

This paper presents a digital centric transmitter architecture with clock domain transition from the baseband clock to a clock derived from the local oscillator of the proposed transmitter. Both clock domains are asynchronous and variable in general, hence this transistion block represents the key building block of the digital signal processing chain. It consists of a synchronizing stage, a timing control unit, and a modified Generalized Farrow upsample filter which allows to implement further upsample stages using simple integer-ratio CIC filters. The architecture is well appropriate for low energy digital-centric hardware designs. Highly reconfigurable, it is applied in a state-of-the-art multimode multistandard transmitter with radio frequency DAC frontend, suitable for WLAN, UMTS, LTE and other recent standards.

Maximum power point tracking (MPPT) techniques are widely applied in photovoltaic (PV) systems to fully utilize the PV array output power. Major challenges for MPPT are rapidly changing irradiance conditions and partial shading of the PV cells. These issues become even more severe for mobile applications, such as solar cells on the roof of electric vehicles. This paper deals with the implementation of a fast, fully integrated MPPT for a small number of solar cells connected in series with respect to mobile applications. For this special requirements, different open and closed loop MPPTs have been compared and evaluated. The optimal MPPT has hence been implemented. Furthermore, a bypass concept based on MOSFETs instead of bypass diodes is applied to utilize the maximum available power of the solar cells. The MPPT has been built in VHDL and realized in a 150nm CMOS technology. Due to its adaptive step size and its high sampling rate, the MPPT reaches the MPP within less than 0.65 ms with consumes less than 6.2 μW.