This article focuses on the economic environmental resource management for islanded Microgrids. To optimize the competing social welfare and environmental impact objectives simultaneously, by using the linear weighted sum method, a switched distributed algorithm is proposed to assign the energy among multiple heterogeneous generation devices and loads. Considering the vulnerability of distributed algorithms to the denial of service (DoS) attacks, we study the impact of the frequency and duration of such attacks on the algorithm performance. To obtain the optimal operation even under DoS attacks, sufficient conditions are presented to ensure the exponential convergence of the algorithm. Meanwhile, an event-triggered communication strategy is designed to reduce communication resource among participants. Finally, the effectiveness of the algorithm is illustrated by several case studies.Note to Practitioners—Resource management problem is a key issue in Microgrids to improve the economics of operation, which can be addressed by distributed cooperative algorithms. As a typical cyber-physical system, the optimality and convergence of the distributed algorithms can be easily disrupted by various cyber-attacks, such as DoS attacks. The existing distributed algorithms are typically implemented under ideal communication environments. To overcome the limitation and accommodate various resources in the future Microgrids, a distributed initialization-free algorithm is proposed that is resilient to DoS attacks. Besides, practitioners can adjust the coefficients of the algorithm based on the real operating situations to guarantee the convergence. Our future work will focus on designing resistance mechanisms and considering more practical constraints.

This article investigates the coordination dual-mode energy management problem (EMP) for a microgrid. First, the islanded and grid-connected modes are modeled into a unified form, which enhances the adaptability and flexibility of the microgrid. Second, a novel distributed algorithm is designed to solve the EMP. By the algorithm, each participant adaptively responds to the change of mode switching and obtains its optimal operation in a distributed way. Besides, compared with the existing distributed energy management algorithms, the convergence time can be predefined exactly by the users, which is independent of any designed parameters and the initial states. Furthermore, the communication strategy is event-triggered, which reduces communication resource consumptions greatly. Finally, simulation results are presented to demonstrate the effectiveness of the designed model and algorithm.

HopliteBuf is a deflection-free, low-cost, and high-speed FPGA overlay Network-on-chip (NoC) with stall-free buffers. It is an FPGA-friendly 2D unidirectional torus topology built on top of HopliteRT overlay NoC. The stall-free buffers in HopliteBuf are supported by static analysis tools based on network calculus that help determine worst-case FIFO occupancy bounds for a prescribed workload. We implement these FIFOs using cheap LUT SRAMs (Xilinx SRL32s and Intel MLABs) to reduce cost. HopliteBuf is a hybrid microarchitecture that combines the performance benefits of conventional buffered NoCs by using stall-free buffers with the cost advantages of deflection-routed NoCs by retaining the lightweight unidirectional torus topology structure. We present two design variants of the HopliteBuf NoC: (1) single corner-turn FIFO ( W → S ) and (2) dual corner-turn FIFO ( W → S + N ). The single corner-turn ( W → S ) design is simpler and only introduces a buffering requirement for packets changing dimension from the X ring to the downhill Y ring (or West to South). The dual corner-turn variant requires two FIFOs for turning packets going downhill ( W → S ) as well as uphill ( W → N ). The dual corner-turn design overcomes the mathematical analysis challenges associated with single corner-turn designs for communication workloads with cyclic dependencies between flow traversal paths at the expense of a small increase in resource cost. Our static analysis delivers bounds that are not only better (in latency) than HopliteRT but also tighter by 2−3×. Across 100 randomly generated flowsets mapped to a 5×5 system size, HopliteBuf is able to route a larger fraction of these flowsets with <128-deep FIFOs, boost worst-case routing latency by ≈ 2× for mutually feasible flowsets, and support a 10% higher injection rate than HopliteRT. At 20% injection rates, HopliteRT is only able to route 1--2% of the flowsets, while HopliteBuf can deliver 40--50% sustainability. When compared to the W → S bkp backpressure-based router, we observe that our HopliteBuf solution offers 25--30% better feasibility at 30--40% lower LUT cost.

Deflection-routed NoCs like Hoplite and HopliteRT take advantage of FPGA-specific features to deliver low-cost, high-frequency, FPGA-friendly communication networks. However, they suffer from long packet deflection penalties, low sustained throughputs, and feature limitations such as out-of-order delivery of packets. In this paper, we introduce the HopliteBuf NoC, and an associated static analysis tool, that eliminates deflections entirely while simultaneously adding in-order delivery feature using (1) small, stall-free FIFOs with provable occupancy bounds, and (2) linearization of vertical rings of the torus Hoplite topology to improve provable link utilization. We implement these FIFOs using cheap LUT SRAMs (Xilinx SRL32s, and Intel MLABs) to absorb packet contention. We evaluate conditions for stall-free behavior using static analysis that compute upper bounds on FIFO occupancy based on the communication pattern. Our static analysis deliver bounds that are not only better (in latency) than HopliteRT but also tighter by 2--3×. Across 100 randomly-generated flowsets mapped to a 5×5 system size, HopliteBuf is able to route a larger fraction of these flowsets with \textless 128-deep FIFOs, boost worst-case routing latency by $\approx$2× for mutually feasible flowsets. At 20% injection rates, HopliteRT is only able to route 1--2% of the flowsets while HopliteBuf can deliver 40--50% sustainability.

Due to increasing demand for computational power, parallel processing is becoming important for real-time systems. The community has proposed and analyzed several task models and scheduling schemes for parallel applications. Gang scheduling, where all threads of the same task are required to run concurrently, can lead to significant execution time improvements for tightly-synchronized applications. However, existing work on real-time gang scheduling for the rigid model assumes that the number of threads of a parallel task remains constant during its execution, which is not the case for many applications. In this paper, we introduce a novel task model where each task is divided into a sequence of segments called bundles, each requiring a different number of cores, and the threads within each bundle are gang scheduled on an identical multiprocessor. We then derive a sufficient schedulability analysis for sporadic bundled tasks under fixed-priority scheduling. Our evaluation reveals that the proposed model can significantly improve schedulability compared to the rigid model while being competitive with non-gang global thread scheduling and federated scheduling.

Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to enable calculation of precise upper bounds on routing latency by modifying the routing function to prioritize deflections, and by regulating the injection of packets to meet certain throughput and burstiness constraints. We provide an analytical model for computing end-to-end latency in the form of (1) in-flight time in the network Tf, and (2) waiting time at the source node Ts. To bound in-flight time in an m × m NoC, we modify the routing function and switching crossbar richness in the Hoplite router to deliver Tf= ΔΧ + ΔΥ + (AY × m) + 2 where AX and ΔΥ are differences of the source and destination address co-ordinates of the packet. To bound the waiting time at the source, we add a Token Bucket regulator with rate ρiand burstiness σifor each flow fiof node (x, y) to deliver (⌈1/ρi⌉ − 1) + Ts: Ts= ⌈σ(ΓCf)/1−σ(ΓCf);⌉ which depends on the regulator period 1/ρi, burstiness a and the rate ρ of all interfering flows ΓCf. A 64b implementation of our HopliteRT router requires ≈4% fewer LUTs, and similar number of FFs compared to the original Hoplite router. We also need two small counters at each client port for regulating injection. We evaluate our model and RTL implementation across synthetic traffic patterns and observe behavior that conforms with the analytical bounds.

The reliable use of multi-core platforms for designing safety-critical systems still represents an open challenge. Recently, the FAA [1] has formally expressed its concern towards the use of multi-core systems in avionics. The sharing of hardware resources introduces non-trivial timing dependencies between logically independent components (e.g. cores); additionally, the increase in size of circuitry, memory resources, and transistor density makes these platforms more susceptible to transient memory (soft) errors. This work addresses the problem of memory soft errors and their recovery at an OS/platform level on commercial multi-core systems. Proposed strategy considers the schedulability impact of recovery procedures on hard real-time workloads. Finally, the implementation of a SPM-centric OS with the proposed OS-level strategies was performed by using a commercially available multi-core platform. The design has been validated and evaluated using a combination of synthetic and realistic (EEMBC) benchmarks.

Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are the shared low level resources, such as the memory hierarchy and the I/O subsystem. In this paper, we approach the problem of shared resource arbitration at an OS-level and propose a novel scratchpad-centric OS design for multi-core platforms. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. Hence, we show (i) how contention-free execution of real-time tasks can be achieved on scratchpad-based architectures, and (ii) how a separation of application logic and I/O perations in the time domain can be enforced. To validate the proposed design, we implemented the proposed OS using a commercial-off-the-shelf (COTS) platform. Experiments show that this novel design delivers predictable temporal behavior to hard real-time tasks, and it improves performance up to 2.1× compared to traditional approaches.

Current computing architectures are commonly built with multiple cores and a single shared main memory. Even though this architecture increases the overall computation power, main memory can easily become a bottleneck. Simultaneous access to main memory from multiple cores can cause both (1) severe degradation in performance and (2) unpredictable execution time for real-time applications. We propose in this paper to mitigate these two problems by co-scheduling cores as well as the main memory for predictable execution. In particular, we use a DMA component to overlap memory with computation for hiding the memory latency and therefore increasing the system performance. The main contribution of this paper is a novel global co-scheduling algorithm along with its associated schedulability analysis for sporadic hard real-time tasks. We evaluated our system by generating synthetic tasksets based on real benchmark parameters. The results show a significant improvement in system utilization while retaining a predictable system behavior.

Modern embedded platforms contain a variety of physical resources, such as caches, interconnects, main memory, etc., which the processor must access during the execution of a task. We argue that processor task execution and accesses to physical resources should be co-scheduled in real-time systems to predictably hide resource access latency. In particular, in this work we focus on co-scheduling task execution and accesses to main memory to hide DRAM access latency. Since modern systems implement DMA controllers that can be operated independently of processor execution, this allows us to hide memory transfer latency by scheduling DMA transfer in parallel with processor execution. The main contribution of this paper is a dynamic scheduling algorithm for a set of sporadic real-time tasks that efficiently co-schedules processor and DMA execution to hide memory transfer latency. The proposed algorithm can be applied to either uniprocessor or partitioned multiprocessor systems. We demonstrate that we improve processor utilization significantly compared to existing scratchpad and cache management systems.

Scratchpad memory is an attractive alternative to caches in real-time embedded systems due to its advantages in terms of timing predictability and power consumption. However, dynamic management of scratchpad content is challenging in multitasking environments. To address this issue, we propose the design of a novel Real-Time Scratchpad Memory Unit (RSMU). Our RSMU can be integrated in existing systems with minimal architectural modifications. Furthermore, scratchpad management is performed at the OS level, requiring no application changes. Compared to existing multitasking scratchpad management schemes, our approach improves schedulability by hiding the latency of memory transfers. We demonstrate and evaluate our system design on an embedded FPGA platform.