Demo Data from SIGIR 2026 / reviewers in the wild / expert
Sébastien Valat
dblp:139/2477
· DBLP profile ↗
2ranked-venue papers
0as first author
1since 2021 · last 2022
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Datacenter networks · 77% Network performance modeling · 23% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Datacenter networks
many-to-one communication |
0.6 | 1 | 2022 | Ethernet for High-Throughput Computing at CERN · IEEE Trans. Parallel Distributed Syst. 2022 |
Network performance modeling › network utilization
link utilization |
0.2 | 1 | 2022 | Ethernet for High-Throughput Computing at CERN · IEEE Trans. Parallel Distributed Syst. 2022 |
Embedded and real-time systems › sensor systems
data acquisition system |
0.2 | 1 | 2022 | Ethernet for High-Throughput Computing at CERN · IEEE Trans. Parallel Distributed Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
performance evaluation · 1.1benchmark testing · 1.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Ethernet for High-Throughput Computing at CERNabstractWhen high throughput and utilization of fabric at close-to-the-link capacity are most needed in a cluster, Ethernet is a potential candidate, rivaling traditional HPC interconnects. The distributed real-time data acquisition at particle physics experiments presents an interesting use case. This article evaluates possible Ethernet-based solutions for aggregating data from hundreds of data sources at a throughput of dozens of Tb/s. This leads us to many-to-one data exchanges where we strive for a cost-optimized setup sustaining more than 80 % of the theoretical link-load. We investigate possible Ethernet-based traffic patterns to handle data acquisition on large multi-source apparatuses. Different numbers of producers and receivers and different link speeds are allowed in a large-scale network. Performance tests were conducted using customized benchmarks and evaluation test benches. The article presents tested scenarios and problems encountered in practice. We describe how our findings influenced the design of a large production system at CERN. We also present relevant general conclusions for a broader range of applications of Ethernet in HPC. Rafal Krawczyk, Tommaso Colombo 0002, Niko Neufeld, Flavio Pisani, Sébastien Valat |
IEEE Trans. Parallel Distributed Syst. | 5 |
| 2019 | uMMAP-IO: User-Level Memory-Mapped I/O for HPCabstractThe integration of local storage technologies alongside traditional parallel file systems on HPC clusters, is expected to rise the programming complexity on scientific applications aiming to take advantage of the increased-level of heterogeneity. In this work, we present uMMAP-IO, a user-level memory-mapped I/O implementation that simplifies data management on multi-tier storage subsystems. Compared to the memory-mapped I/O mechanism of the OS, our approach features per-allocation configurable settings (e.g., segment size) and transparently enables access to a diverse range of memory and storage technologies, such as the burst buffer I/O accelerators. Preliminary results indicate that uMMAP-IO provides at least 5-10x better performance on representative workloads in comparison with the standard memory-mapped I/O of the OS, and approximately 20-50% degradation on average compared to using conventional memory allocations without storage support up to 8192 processes. Sergio Rivas-Gomez, Alessandro Fanfarillo, Sébastien Valat, Christophe Laferriere, Philippe Couvée, Sai Narasimhamurthy, Stefano Markidis |
HiPC | 3 |