We present two efficient imaged-based approaches for computation and display of high-quality soft shadows from area light sources. Our methods are related to shadow maps and provide the associated benefits. The computation time and memory requirements for adding soft shadows to an image depend on image size and the number of lights, not geometric scene complexity. We also show that because area light sources are localized in space, soft shadow computations are particularly well suited to imaged-based rendering techniques. Our first approach—layered attenuation maps—achieves interactive rendering rates, but limits sampling flexibility, while our second method—coherence-based raytracing of depth images—is not interactive, but removes the limitations on sampling and yields high quality images at a fraction of the cost of conventional raytracers. Combining the two algorithms allows for rapid previewing followed by efficient high-quality rendering.

We have implemented an image combining architecture that allows distributed rendering of a partitioned data set at interactive rates. The architecture achieves real-time frame rates and low latency through pipelining and the use of a high bandwidth network technology to transfer the image data. It is flexible because it uses programmable FPGA devices to implement the combining logic. The implementation cost is kept low by using only commodity components for the network and graphics, and FPGA logic. The result is a cost-effective interactive visualization system that can be used with a variety of applications running on distributed computing systems such as cluster of workstations and personal computers. We first motivate the development of a distributed rendering system and we introduce some of the concepts related to the 3D-visualization domain. We then describe our implementation of this system using the PCI Pamette FPGA-based board. We emphasize the advantages of using a programmable board for the prototype development and also for a potential commercial version.

A polarimetry system for solar astronomy is presented. The system is based on a reconfigurable coprocessor attached to a conventional workstation. Although the computationally intensive parts of the application are performed in the host processor the reconfigurable coprocessor plays a key role in taking charge of tasks that the host performs poorly, such as cycle-by-cycle data marshalling and real-time synchronization. The runtime environment supporting the reconfigurable coprocessor makes it easy to experiment with different implementation tradeoffs and postpone the final partitioning of functionality between the host and reconfigurable coprocessor until quite late in the design process.

We describe the use of a reconfigurable board to obtain information on the performance that can be expected on particular systems. Our goal is to use the reconfigurability, of the board's interface to test a system and discover not only the maximum bandwidth and best latency attainable, but also the way to reliably achieve these figures. The board we present uses the now widespread PCI bus. PCI is sufficiently complex, and its implementations sufficiently varied, that it is impossible to guess the performance that can be obtained by a specific board on a specific computer with the only technical characteristics of the two in hand. We observe astonishing performance differences between almost identical systems and comparable figures between small PCs and big servers. Our performance tests can be an end in themselves, however, they also serve to demonstrate the value of a reconfigurable bus interface. With the same board, we can test and choose a system, make informed architectural decisions on the hardware/software interface, and then finely tune the bus interface to get maximum and predictable figures in the running application.

The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DEC-PRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1 [2]. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.