In the Internet of Things (IoT) ecosystem, optimizing processing capabilities of devices through Wireless Powered Mobile Edge Computing (WP-MEC) is crucial. This research addresses the challenge of efficiently scheduling task offloading from devices to an edge server, which is vital for enhancing system performance. Prior studies often overlook the necessity for rapid adaptation to changing wireless conditions, resulting in suboptimal offloading strategies. Our work introduces the Intelligent Online Computation Offloading (IOCO) algorithm, leveraging Deep Neural Networks (DNNs) to make informed, real-time offloading decisions based on previous experiences. This approach not only optimizes the allocation of wireless and computing resources but also incorporates novel quantization and sampling methods to improve robustness and adaptability. Simulation results demonstrate that IOCO can achieve near-optimal efficiency swiftly and adapt effectively to significant resource changes, highlighting its practicality in dynamic WP-MEC environments.

The real-valued fast Fourier transform (RFFT) is an ideal candidate for implementing a high-speed and low-power FFT processor because it only has approximately half the num-ber of arithmetic operations compared with traditional complex-valued FFT (CFFT). Although RFFT can be calculated using CFFT hardware, a dedicated RFFT implementation can result in reduced hardware complexity, power consumption and increased throughput. However, unlike CFFT, RFFT has irregular signal flow graphs which hinders the design of efficient pipelined archi-tectures. In this paper, utilizing Open Computing Language (OpenCL), we propose a high-level programming method for the implementation of pipelined architectures of RFFT on FPGAs. By identifying the regular computational pattern in the flow graph of RFFT, the proposed method essentially uses a for loop to implement the RFFT algorithm, and later with the help of high level synthesis tools, the loop is fully unrolled to automatically build pipelined architectures. Experiments show that for a 4096-point RFFT, the proposed method achieves a 2.49x speedup and 3.09x better energy efficiency over CUFFT on GPU, and a 21.12x speedup and 16.09x better energy efficiency over FFTW on CPU respectively. Compared to Intels CFFT design on the same FPGA, the proposed one reduces 12% logic resources and 16% DSP blocks respectively, while achieving a 1.48x speedup.

In Internet of Vehicles, task processing performance of vehicle is always limited by its finite energy and low computing power. Wireless Powered Vehicular Edge Computing (WP-VEC) is a solution to this limitation, where vehicles can harvest energy and offload tasks. However, many related works pay less attention to timeliness of offloading strategy, and thus suffer poor adaptability to highly dynamic environments. In this paper, we consider a WP-VEC network with binary offloading decision. We jointly optimize offloading decision and resource allocation to minimize weighted sum of delay. Here, the resource allocation includes time allocation between energy harvesting phase and offloading phase, and communication and computation resource allocation in offloading phase. This problem is formulated as a Mixed Integer Programming (MIP) problem, which is hardly to be solved within channel coherence time by traditional methods. To overcome this, we utilize deep neural network and optimization technologies to design such an Intelligent Online Computation Offloading (IOCO) algorithm. Simulation results verify its excellent performance on effectiveness, convergence, and robustness, which verifies IOCO can adapt to highly dynamic environments.

Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of SRFFT is the same as radix-2 FFT, and therefore, the conventional address generation schemes of FFT data could also be applied to SRFFT. However, SRFFT has irregular locations of twiddle factors and forbids the application of radix-2 address generation methods. This brief presents a shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by using a modified radix-2 butterfly unit. The butterfly unit exploits the multiplier-gating technique to save dynamic power at the expense of using more hardware resources. In addition, two novel address generation algorithms for both the trivial and nontrivial twiddle factors are developed. Simulation results show that compared with the conventional radix-2 shared-memory implementations, the proposed design achieves over 20% lower power consumption when computing a 1024-point complex-valued transform.

Split-Radix Fast Fourier Transform (SRFFT) has the lowest number of arithmetic operations among all the FFT algorithms. Since arithmetic operations dramatically contribute to the dynamic power consumption, SRFFT is an ideal candidate for the implementation of a low power FFT processor. In the design of such processors, an efficient addressing scheme for FFT data as well as coefficients is required. The signal flow graph of split-radix algorithm is the same as radix-2 FFT except for the location and value of coefficients, therefore conventional radix-2 FFT data address generation scheme could also be applied to SRFFT. However, the mixed radix property of SRFFT algorithm leads to irregular locations of coefficients and forbids any conventional address generation algorithm. This paper presents a novel coefficient address generation algorithm for shared-memory based SRFFT processor. The core part of the proposed algorithm is to use two control variables to track trivial and non-trivial multiplications. We found the relationship between the value of the control variables and the butterfly and pass counter. The corresponding hardware implementation is simple consisting of a shift register and a dual port RAM bank. Compared to look-up table approach, which pre-computes the addresses of all coefficients and stores the addresses in memory units, the proposed algorithm is scalable and only requires small amount of memory to find the correct addresses of coefficients.

Fast Fourier Transform (FFT) is one of the fundamental operations in digital signal processing area. Split-radix Fast Fourier Transform (SRFFT) approximates the minimum number of multiplications by theory among all the FFT algorithms, therefore SRFFT is a good candidate for the implementation of a low power FFT processor. In this PhD work, we aim to implement a novel low power Split-Radix FFT processor using shared-memory architecture and extend this work to a parallel structure based on FPGA. We started by designing a new radix-2 butterfly unit using clock gating approach to block unnecessary switching activity in the multiplier. Compared to existing SRFFT processors which are based on the “L” shaped butterfly, our implementation simplifies the address generation process for FFT data. Furthermore, because the number of multiplications required by SRFFT algorithm significantly decreases as the FFT size increases, it is reasonable to assume the proposed architecture will save more power when it comes to larger points of FFT.

Split-radix Fast Fourier Transform (SRFFT) approximates the minimum number of multiplications by theory among all the FFT algorithms. Since multiplications significantly contribute to the overall system power consumption, SRFFT is a good candidate for implementation of a low power FFT processor. In this paper we present a novel low power SRFFT processor using a modified radix-2 butterfly structure. With the proposed butterfly unit, the address generation scheme for conventional radix-2 FFT could be applied to SRFFT and therefore it can avoid the complexity of address generation and interim data registers. Simulation results show that compared with a conventional radix-2 implementation, power consumption of the new processor is reduced by an amount of 11.7% and 18.3% for 16-point and 32-point FFT respectively.