Demo Data from SIGIR 2026 / reviewers in the wild / expert
Romain Poussier
dblp:146/7920
· DBLP profile ↗
8ranked-venue papers
4as first author
1since 2021 · last 2025
0009-0004-2255-4087ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 7 · 4 first-authorSystems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
3 papers |
Hardware security and side channels · 79% Cryptographic primitives and cryptanalysis · 21% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 9 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › side-channel attack
power analysis |
0.9 | 1 | 2025 | PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance · ACM Trans. Archit. Code Optim. 2025 |
Hardware security and side channels › side-channel countermeasures
power analysis countermeasure |
0.9 | 1 | 2025 | PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance · ACM Trans. Archit. Code Optim. 2025 |
Processor architecture and microarchitecture
instruction scheduling |
0.9 | 1 | 2025 | PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance · ACM Trans. Archit. Code Optim. 2025 |
Processor architecture and microarchitecture › out-of-order execution
out-of-order processor |
0.9 | 1 | 2025 | PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance · ACM Trans. Archit. Code Optim. 2025 |
Hardware security and side channels
side-channel attack |
0.3 | 1 | 2017 | A Systematic Approach to the Side-Channel Analysis of ECC Implementations with Worst-Case Horizontal Attacks · CHES 2017 |
Cryptographic primitives and cryptanalysis › block cipher
AES |
0.3 | 1 | 2025 | PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance · ACM Trans. Archit. Code Optim. 2025 |
Hardware security and side channels › side-channel countermeasures
masking |
0.3 | 1 | 2025 | PARADISE: Criticality-Aware Instruction Reordering for Power Attack Resistance · ACM Trans. Archit. Code Optim. 2025 |
Cryptographic primitives and cryptanalysis › generic attacks
exhaustive key search |
0.2 | 1 | 2016 | Simple Key Enumeration (and Rank Estimation) Using Histograms: An Integrated Approach · CHES 2016 |
Cryptographic primitives and cryptanalysis › public-key cryptography
elliptic curve cryptography |
0.1 | 1 | 2017 | A Systematic Approach to the Side-Channel Analysis of ECC Implementations with Worst-Case Horizontal Attacks · CHES 2017 |
Methods — techniques the papers use, named apart from their topics
dynamic instruction reordering · 1.7boolean masking · 1.7CNN-based attack · 1.7side-channel analysis · 0.3histogram-based key enumeration · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | PARADISE: Criticality-Aware Instruction Reordering for Power Attack ResistanceabstractPower side-channel attacks exploit the correlation of power consumption with the instructions and data being processed to extract secrets from a device (e.g., cryptographic keys). Prior work primarily focused on protecting small embedded micro-controllers and in-order processors rather than high-performance, out-of-order desktop and server CPUs. In this article, we present Paradise , a general-purpose out-of-order processor with always-on protection, that implements a novel dynamic instruction scheduler to provide obfuscated execution and mitigate power analysis attacks. To achieve this, we exploit the time between operand availability of critical instructions ( slack ) and create high-performance random schedules. Further, we highlight the dangers of using incorrect adversarial assumptions, which can often lead to a false sense of security. Therefore, we perform an extended security analysis on AES-128 using different levels of adversaries, from basic to advanced, including a convolution neural networks–based attack. Our advanced security evaluation assumes a strong adversary with full knowledge of the countermeasure and demonstrates a significant security improvement of 556 × when combined with Boolean Masking over a baseline only protected by masking and 62,500× over an unprotected baseline. The resulting overhead in performance, power, and area of Paradise is 3.2%, 1.2%, and 0.8% respectively. 1 Yun Chen 0004, Ali Hajiabadi, Romain Poussier, Yaswanth Tavva, Andreas Diavastos, Shivam Bhasin, Trevor E. Carlson |
ACM Trans. Archit. Code Optim. | 3 |
| 2019 | Key Enumeration from the Adversarial Viewpoint
Melissa Azouaoui, Romain Poussier, François-Xavier Standaert, Vincent Verneuil |
CARDIS | 2 |
| 2017 | Connecting and Improving Direct Sum Masking and Inner Product Masking
Romain Poussier, Qian Guo 0001, François-Xavier Standaert, Claude Carlet, Sylvain Guilley |
CARDIS | 1 |
| 2017 | A Systematic Approach to the Side-Channel Analysis of ECC Implementations with Worst-Case Horizontal Attacks
Romain Poussier, Yuanyuan Zhou 0006, François-Xavier Standaert |
CHES | 1 |
| 2016 | Simple Key Enumeration (and Rank Estimation) Using Histograms: An Integrated Approach
Romain Poussier, François-Xavier Standaert, Vincent Grosso |
CHES | 1 |
| 2015 | Comparing Approaches to Rank Estimation for Side-Channel Security Evaluations
Romain Poussier, Vincent Grosso, François-Xavier Standaert |
CARDIS | 1 |
| 2015 | Simpler and More Efficient Rank Estimation for Side-Channel Security Assessment
Cezary Glowacz, Vincent Grosso, Romain Poussier, Joachim Schüth, François-Xavier Standaert |
FSE | 3 |
| 2014 | Combining Leakage-Resilient PRFs and Shuffling - Towards Bounded Security for Small Embedded Devices
Vincent Grosso, Romain Poussier, François-Xavier Standaert, Lubos Gaspar |
CARDIS | 2 |