Fixed-priority (FP) scheduling is widely used in safety-critical real-time systems due to its simplicity and analyzability, yet it may fail to schedule task sets whose worst-case response-time bounds exceed deadlines by small margins. Meanwhile, modern processors increasingly support short-term frequency boosting, providing additional processing capacity subject to thermal and power constraints. This paper introduces Boosted-FP, a fixed-priority scheduling framework that augments a given FP policy with controlled, limited frequency boosting. The key idea is to activate boosting based on the worst-case remaining execution demand of the currently executing job, thereby confining high-frequency execution to the tail of jobs. Per-task boost parameters are computed offline using standard fixed-priority response-time analysis under the chosen priority assignment, while boost activation decisions are made online using worst-case remaining-work information. We show that Boosted-FP preserves hard real-time guarantees by relating its execution behavior to that of a task set with reduced execution times. Leveraging the sustainability of fixed-priority schedulability analysis with respect to execution-time reductions, we establish that any task set schedulable under the modified execution bounds is also schedulable under the proposed framework. We evaluate the framework under a global boost-budget constraint and show experimentally that boost usage remains bounded and often well below the offline provisioned budget. Together, these results demonstrate that controlled, work-triggered boosting can safely extend the schedulable region of fixed-priority scheduling without abandoning static priorities.

Aggressive scaling in integrated circuits creates new challenges such as an increase in power density, temperature, and especially process variation in designing Multiprocessor Systems-on-Chip (MPSoC). While most of the previous works attempt to mitigate the process variation effects at the system level, the eventual design still suffers from the variability of frequency and leakage power. In this paper, we propose a method calledStereothat combinesstochastic and decomposition to solve task assignment and scheduling under process variation in MPSoCs. In our previous work, we formulated a Mixed Integer Linear Programming (MILP) problem for variation-aware task assignment and scheduling to optimize energy consumption while meeting the real-time constraints. To capture the stochastic behavior of process variation, we employed a chance-constrained programming technique to turn the problem into a corresponding stochastic optimization that can be solved by typical ILP solvers. However, it had a scalability problem. To address this issue, in this work, we leverage a Logic-based Benders Decomposition (LBD) approach to improve the running time for finding an optimal solution of assignments and schedulings under process variation phenomenon). We carried out extensive experiments using Embedded System Synthesis Benchmarks Suite (E3S). The experimental results of the Stereo method evince considerable improvements compared to the baseline method in terms of performance-yield and run-time. The Stereo-based MILP method ameliorates performance-yield up to 2× and run-time by 532×. Moreover, for manifold applications, the Stereo-based LBD method archives 3.47×-91.49× run-time improvement compared to the Stereo-based MILP approach and is capable of assigning and scheduling of more than 50 tasks on 9 processors.

Nowadays, aggressive scaling in integrated circuits brings out new challenges such as increase in power density, temperature, and process variation in designing Multiprocessor Systems-on-Chip (MPSoC) employed in embedded systems. While most of the previous works attempt to mitigate the process variation effects in system design level, the eventual design still is inefficient and suffers from the variability of frequency and leakage power of processors in a MPSoC. In this paper, we formulate a MILP problem for variation-aware task assignment and scheduling to optimize power consumption while meeting the real-time constraints. To capture stochastic behavior of process variation, we employ chance-constrained programming technique to turn the problem into a corresponding stochastic optimization one that can be solved by typical solvers. Extensive experiments using E3S benchmarks have been carried out and the obtained results of the proposed method evince improvements compared to the baseline method in terms of performance-yield and run-time.

Due to unreliability of the cores in embedded systems in deep sub-micron technologies, a method for testing cores in the field is needed. In this paper an online method for testing cores of embedded designs is presented. The proposed task scheduling method runs the test routine ASAP periodically considering the real time constraints. A software test routine based on a proposed method will be generated and a task scheduling process including the test task (for each core) and other existing applications of the embedded system will be presented. A software based checksum is issued for online test result analysis that shortens the memory usage of the test process. Experimental results show that this method improves the test application time (TAT) and fault coverage (in proportion to TAT) as compared with the existing methods.