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Mutsumi Kimura

dblp:15/4916 · DBLP profile ↗
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10ranked-venue papers
7as first author
2since 2021 · last 2024
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 9 · 6 first-author · 2 since 2021Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Electronic design automation · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.012002
Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Integrated circuit design › analog and mixed-signal circuits
device modeling
0.012002
Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002
Integrated circuit design › semiconductor device modeling
thin-film transistor modeling
0.012002
Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x) · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2002

Methods — techniques the papers use, named apart from their topics

table look-up model · 0.0spline interpolation · 0.0
YearPublicationVenuePosition
2024 Fusion synapse by memristor and capacitor for spiking neuromorphic systems
Takumi Kuwahara, Reon Oshio, Mutsumi Kimura, Yasuhiko Nakashima
Neurocomputing3
2023 Neuromorphic System Using Memcapacitors and Autonomous Local Learning
abstract
Artificial intelligence is used for various applications and is promising as an indispensable infrastructure in future societies. Neural networks are representative technologies that imitate human brains and exhibit various advantages. However, the size is bulky, the power is huge, and some advantages are not demonstrated because they are executed on Neumann-type computers. Neuromorphic systems are biomimetic systems from the hardware level to implement neuron and synapse elements, and the size is compact, the power is low, and the operation is robust. However, because the conventional ones are not composed of fully optimized hardware, the power is not yet minimal, and extra control circuits must be used. In this article, we developed a neuromorphic system using memcapacitors and autonomous local learning. By using memcapacitors, the power can be minimal, and by using autonomous local learning, the control circuits to handle the synapse elements can be deleted. First, the memcapacitors are completed in a cross-bar array, where the ferroelectric layers are sandwiched between the horizontal and perpendicular electrodes. The polarization and capacitance exhibit hysteresis due to the dielectric polarization. Next, autonomous local learning is introduced as follows. During the training phase, associative patterns to be memorized are directly sent, relatively high voltages are applied, and dielectric polarizations are induced. During the operation phase, relatively low voltages are applied, and input signals are weighted with the capacitances of the memcapacitors, summed, and transferred as the output signals. Finally, the experimental system is set up, and the experimental results are acquired. The memorized patterns during the training phase, distorted patterns as the input signals during the operation phase, and retrieved patterns as the output signals in the operation phase are shown. Researchers found that the retrieved patterns are completely the same as the memorized patterns. This means that the neuromorphic system works as an associative memory.
Mutsumi Kimura, Yuma Ishisaki, Yuta Miyabe, Homare Yoshida, Isato Ogawa, Tomoharu Yokoyama, Ken-Ichi Haga, Eisuke Tokumitsu, Yasuhiko Nakashima
IEEE Trans. Neural Networks Learn. Syst.1
2019 Neuro-inspired System with Crossbar Array of Amorphous Metal-Oxide-Semiconductor Thin-Film Devices as Self-plastic Synapse Units
Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
ICONIP (2)1
2018 Hopfield Neural Network with Double-Layer Amorphous Metal-Oxide Semiconductor Thin-Film Devices as Crosspoint-Type Synapse Elements and Working Confirmation of Letter Recognition
Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
ICONIP (7)1
2017 Neuromorphic Hardware Using Simplified Elements and Thin-Film Semiconductor Devices as Synapse Elements - Simulation of Hopfield and Cellular Neural Network -
Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima
ICONIP (6)2
2017 Cellular neural network formed by simplified processing elements composed of thin-film transistors
Mutsumi Kimura, Ryohei Morita, Sumio Sugisaki, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
Neurocomputing1
2016 Letter Reproduction Simulator for Hardware Design of Cellular Neural Network Using Thin-Film Synapses - Crosspoint-Type Synapses and Simulation Algorithm
Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima
ICONIP (2)2
2016 Simplification of Processing Elements in Cellular Neural Networks - Working Confirmation Using Circuit Simulation
Mutsumi Kimura, Nao Nakamura, Tomoharu Yokoyama, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima
ICONIP (2)1
2015 Novel Architecture for Cellular Neural Network Suitable for High-Density Integration of Electron Devices-Learning of Multiple Logics
Mutsumi Kimura, Yusuke Fujita, Tomohiro Kasakawa, Tokiyoshi Matsuda
ICONIP (1)1
2002 Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x)
abstract
A table look-up model of thin-film transistors has been developed for circuit simulation. This model utilizes three schemes. First, the spline interpolation with transformation by y = x+log(x) achieves precision for both on-current and off-current simultaneously. Second, the square polynomial supplement solves an anomaly near the points where drain voltage equals zero. Third, the linear extrapolation achieves continuities of the current and its derivatives as a function of voltages for areas outside where the spline interpolation is performed and improves convergence during circuit simulation.
Mutsumi Kimura, Satoshi Inoue, Tatsuya Shimoda
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1