Demo Data from SIGIR 2026 / reviewers in the wild / expert
Neus Vidal
dblp:151/5635
· DBLP profile ↗
4ranked-venue papers
0as first author
1since 2021 · last 2022
0000-0001-9445-7447ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Integrated circuit design · 62% Electronic design automation · 38% | |
| Theoretical computer science
2 papers |
Mathematical optimization · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
analog and RF circuit synthesis |
0.5 | 2 | 2017 | An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Integrated circuit design
radio-frequency circuit design |
0.5 | 2 | 2017 | An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Integrated circuit design › radio-frequency circuit design
low noise amplifier |
0.3 | 1 | 2017 | An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Mathematical optimization
multi-objective optimization |
0.1 | 2 | 2017 | An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Mathematical optimization › multi-objective optimization
pareto front |
0.1 | 1 | 2017 | An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Methods — techniques the papers use, named apart from their topics
multi-objective optimization · 1.0electromagnetic simulation · 1.0pareto-optimal front · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission linesabstractThis paper presents a 3D topology for high miniaturization of the well-known hybrid branch-line coupler at the UHF band. A preliminary work already proposed the use of helical-microstrip TLs combined with a folded structure for this purpose. This extended work includes a compactness enhancement by loading the TL segments with capacitors. An study of loaded helical-microstrip TL is reported as well. The coupler prototypes have been simulated and fabricated by using a combination of Additive Manufacturing and copper electroplating. The performance results have been compared to the conventional model showing a good agreement. In order to place the designed devices within the state of the art a figure of merit that combines the compactness and the relative bandwidth has been proposed, showing very good results in terms of miniaturization. Arnau Salas Barenys, Neus Vidal, José María López-Villegas |
Integr. | 2 |
| 2018 | Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández 0001 |
Integr. | 4 |
| 2017 | An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated InductorsabstractA new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a singleobjective and a multiobjective optimization of a low noise amplifier. Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández 0001, Javier J. Sieiro, José María López-Villegas, Neus Vidal |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 7 |
| 2014 | Automated Generation of the Optimal Performance Trade-Offs of Integrated InductorsabstractIn this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable. Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández 0001, Javier J. Sieiro, Neus Vidal, José María López-Villegas |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 6 |