Demo Data from SIGIR 2026 / reviewers in the wild / expert
Saumya Bhadauria
dblp:152/3412
· DBLP profile ↗
8ranked-venue papers
0as first author
2since 2021 · last 2022
0000-0002-6502-2695ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4Artificial intelligence and machine learning · 2Computer networks · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Embedded and real-time systems · 50% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
hardware trojan |
0.3 | 1 | 2017 | TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Electronic design automation
high-level synthesis |
0.3 | 1 | 2017 | TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Embedded and real-time systems › real-time scheduling
security-aware scheduling |
0.3 | 1 | 2017 | TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017 |
Methods — techniques the papers use, named apart from their topics
particle swarm optimization · 0.6loop unrolling · 0.6dual modular redundancy · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | A Guided Approach Towards Complex Chaos Selection, Prioritisation and InjectionabstractThough Chaos Engineering is a popular method to test reliability and performance assurance, available tools can only inject random or manually curated faults into a target system. Given the vast array of faults that can be injected, it is crucial to a.) intelligently pick the faults that can have tangible effects, b.) increase the test coverage, and c.) reduce the overall time needed to assess the reliability of a system under adverse conditions. To the effect, we are proposing to learn from past major outages and use genetic algorithm-based meta-heuristics to evolve complex fault injections. Ojaswa Sharma, Mudit Verma, Saumya Bhadauria, Praveen Jayachandran |
CLOUD | 3 |
| 2022 | A cost aware topology formation scheme for latency sensitive applications in edge infrastructure-as-a-service paradigm
Himanshu Gauttam, Kiran Kumar Pattanaik, Saumya Bhadauria, Divya Saxena, Sapna |
J. Netw. Comput. Appl. | 3 |
| 2017 | Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper)
Anirban Sengupta 0003, Dipanjan Roy, Saumya Bhadauria |
Integr. | 3 |
| 2017 | TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level SynthesisabstractSecurity against hardware Trojan that is capable to change the computational output value is accomplished by employing dual modular redundant (DMR) schedule during high level synthesis (HLS). However, building a DMR for Trojan security is nontrivial and incurs extra delay and hardware. This paper proposes a novel HLS methodology for constraint driven low cost hardware Trojan secured DMR schedule design for loop-based control data flow graphs (CDFGs). Proposed approach simultaneously explores an optimal schedule and optimal loop unrolling factor (U) combination for a low cost Trojan security aware DMR schedule. As a specific example, proposed low cost Trojan secured HLS approach relies on particle swarm optimization algorithm to explore optimized Trojan secured schedule with optimal unrolling that provides security against specific Trojan (causing change in computational output) within user provided area and delay constraints. The novel contributions of this paper are, first an exploration of a low cost Trojan security aware HLS solution for loop-based CDFGs; second, proposed encoding scheme for representing design solution comprising candidate schedule resources, candidate loop unrolling factor and candidate vendor allocation information; third, a process for exploring the a low cost vendor assignment that provides Trojan security; finally, experimental results over the standard benchmark that indicates an average reduction in final cost of ~12% compared to recent approach. Anirban Sengupta 0003, Saumya Bhadauria, Saraju P. Mohanty |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2016 | Embedding low cost optimal watermark during high level synthesis for reusable IP core protectionabstractIntellectual property (IP) cores have emerged as a promising solution to the challenges of future design as well as mounting time to market pressure. However, due to increasing globalization of design supply chain, possibility of intervention and typical attacks is on the rise, which therefore mandates protection of IP cores from piracy/counterfeiting even at behavioral level. This paper presents a technique for generating low cost watermarking solution during high level synthesis (HLS) based on multi-variable signature encoding for security of reusable IP cores. The watermark generated by the proposed approach satisfies the following properties: (a) low embedding cost (b) robustness (c) low watermark creation time (d) strong proof of authorship (e) lower hardware overhead. Comparison with similar technique revealed that proposed approach obtains watermarked solution with lower embedding cost with less storage overhead and creation time. Anirban Sengupta 0003, Saumya Bhadauria, Saraju P. Mohanty |
ISCAS | 2 |
| 2015 | Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level SynthesisabstractAn evolutionary algorithm (EA) driven novel design space exploration (DSE) of an optimized hardware Trojan secured datapath based on user power-delay constraint during high level synthesis (HLS) is presented. The focus on hardware Trojan secured datapath generation during HLS has been very little with absolutely zero effort so far in design space exploration of a user multi-objective (MO) constraint optimized hardware Trojan secured datapath. This problem mandates attention as producing a Trojan secured datapath is not inconsequential. Merely the detection process of Trojan is not as straightforward as concurrent error detection (CED) of transient faults as it involves the concept of multiple third party intellectual property (3PIP) vendors to facilitate detection, let aside the exploration process of a user optimized Trojan secured datapath based on MO constraints. The proposed DSE for hardware Trojan detection includes novel problem encoding technique that enables exploration of efficient distinct vendor allocation as well as enables exploration of an optimized Trojan secured datapath structure. The exploration backbone for the proposed approach is bacterial foraging optimization algorithm (BFOA) which is known for its adaptive feature (tumbling/swimming) and simplified model. Results of comparison with recent approach indicated an average improvement in quality of results (QoR) of >14.1% Anirban Sengupta 0003, Saumya Bhadauria |
ACM Great Lakes Symposium on VLSI | 2 |
| 2015 | Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis
Anirban Sengupta 0003, Saumya Bhadauria |
Expert Syst. Appl. | 2 |
| 2014 | Exploration of Multi-objective Tradeoff during High Level Synthesis Using Bacterial Chemotaxis and DispersalabstractA novel application of bacterial foraging optimization algorithm (BFOA) in the area of design space exploration (DSE) of datapath in high level synthesis (HLS) is presented in this paper. The BFOA has been transformed into an adaptive automated DSE framework that is capable to handle tradeoffs between area-execution time during HLS. To the authors belief, no such application (or transformation) of BFOA into DSE exist in the literature. The key sub-contributions of the proposed approach can be classified as follows: i) Exploration drift using a novel chemotaxis algorithm ii) Diversity introduction in resource configuration using a novel dispersal algorithm iii) Performance analysis of proposed and related approaches on metrics such as generational distance, maximum pareto-optimal front error, spacing, spreading and weighted metric. Finally, results indicated an average improvement in Quality of Results (QoR) of ∼6% and reduction in exploration runtime of > 18% compared to three recent approaches based on PSO and GA. Anirban Sengupta 0003, Saumya Bhadauria |
KES | 2 |