The Internet of Things (IoT) with its plethora of applications brings up new challenges in optimizing power consumption, error performance, latency, and throughput in its communication devices. Recently, there has been increasing necessity of reconfigurable and multistandard transceivers in order to bring adaptability in the IoT devices to suit the nature of the application and satisfy the aforementioned performance metrics as well. In this paper, we focus on the efficient design of receivers compliant with IEEE 802.15.4 which is a prominent protocol for low power IoT applications. We propose a robust phase noise compensation method which efficiently removes the residual phase noise remaining after the coarse frequency offset compensation due to direct-sequence spread spectrum operation on large packets. We also propose a dual-mode receiver using the proposed compensation method and showcase its ability to cater to the diverse nature of IoT applications. The detailed architecture of proposed dual-mode receiver is presented along with its FPGA prototyping and ASIC implementation. We have analyzed overall power consumption by the proposed dual-mode receiver considering the packet error rate and retransmission scenario. The results show that the proposed receiver saves significant energy consumption by changing its mode in favorable channel environments.

In this letter, we propose two novel methods for four-class motor imagery (MI) classification using electroencephalography (EEG). Also, we developed a real-time health 4.0 (H4.0) architecture for brain-controlled internet of things (IoT) enabled environments (BCE), which uses the classified MI task to assist disabled persons in controlling IoT-enabled environments such as lighting and heating, ventilation, and air-conditioning (HVAC). The first method for classification involves a simple and low-complex classification framework using a combination of regularized Riemannian mean (RRM) and linear SVM. Although this method performs better compared to state-of-the-art techniques, it still suffers from a nonnegligible misclassification rate. Hence, to overcome this, the second method offers a persistent decision engine (PDE) for the MI classification, which improves classification accuracy (CA) significantly. The proposed methods are validated using an in-house recorded four-class MI data set (data set I, collected over 14 subjects), and a four-class MI data set 2a of BCI competition IV (data set II, collected over 9 subjects). The proposed RRM architecture obtained average CAs of 74.30% and 67.60% when validated using datasets I and II, respectively. When analyzed along with the proposed PDE classification framework, an average CA of 92.25% on 12 subjects of data set I and 82.54% on 7 subjects of data set II is obtained. The results show that the PDE algorithm is more reliable for the classification of four-class MI and is also feasible for BCE applications. The proposed low-complex BCE architecture is implemented in real time using Raspberry Pi 3 Model B+ along with the Virgo EEG data acquisition system. The hardware implementation results show that the proposed system architecture is well suited for body-wearable devices in the scenario of Health 4.0. We strongly feel that this study can aid in driving the future scope of BCE research.

Recent advances in the Brain-Computer Interface (BCI) systems state that the accurate Motor Imagery (MI) classification using Electroencephalogram (EEG) plays a vital role. In this paper, we propose a novel real-time feature extraction and classification architecture for four class MI using a combination of Kullback-Leibler Regularized Riemannian Mean (KLRRM) and Linear SVM. By using the KL regularization, the robustness of the features extracted to the noise and outliers is improved. The performance of the proposed architecture is analyzed on the four class MI dataset 2a from the BCI Competition IV. The performance analysis shows that the proposed architecture achieves an average classification accuracy of 74.43% and 51.53% for both the good and noisy subjects respectively. Also, the emphasis is laid on understanding the performance of regularization, and the improvement of robustness to the noise and outliers is demonstrated using the noisy subjects.

Brain Computer Interface (BCI) has recently gained much popularity due to plethora of its applications. In this paper, we propose a novel system architecture to utilize brain signals for controlling Internet of Things enabled environments. The proposed architecture aids in translating brain signals to commands that interact with or control the environment using IoT actuation networks thus executing user desired actions. It comprises of novel, low complex and low power intelligent signal processing architecture for detection of voluntary eye blinks by isolating involuntary eye blinks and IoT enabled wireless actuation network for controlling the environment using commands generated from EEG signal. For the real time performance analysis of the proposed architecture, we developed a wearable device which acquires dual channel EEG using electrodes at Fp1 and Fp2 locations. From the acquired EEG data, the device detects the voluntary eye blinks of the patient and use this information in controlling the environment such as switching HVAC system, lighting or electric fan etc. Performance analysis shows that the proposed intelligent signal processing architecture detects the voluntary eye blinks with 95.2% accuracy when tested on 10 subjects with a low power consumption of 165 mW.

With the proliferation of Internet of Things (IoT), the IEEE 802.15.4 physical layer is becoming increasingly popular due to its low power consumption. However, secure data communication over the network is a challenging issue because vulnerabilities in the existing security primitives lead to several attacks. The mitigation of these attacks separately adds significant computing burden on the legitimate node. In this paper, we propose a secure IEEE 802.15.4 transceiver design that mitigates multiple attacks simultaneously by using a physical layer encryption approach that reduces the computations at the upper layers. In addition to providing confidentiality and integrity services, the proposed transceiver provides sufficient complexity to various attacks, such as cryptanalysis and traffic analysis attacks. It also significantly improves the lifetime of the node in the presence of a ghost attacker by preventing the legitimate node from processing the bogus messages and hence combats against energy depletion attacks. The simulation results show that a high symbol error rate at the adversary can be achieved using the proposed transceiver without affecting the throughput at the legitimate node. In this paper, we also analyze the hardware complexity by developing an FPGA and ASIC prototype of the proposed transceiver.