In order to meet the latency requirements of the ultra-reliable low latency communication (URLLC) mode of the third-generation partnership project's long term evolution (LTE) mobile communication standard, this paper proposes a novel turbo decoding algorithm that supports an arbitrarily high degree of parallel processing, facilitating significantly higher processing throughputs and substantially lower processing latencies than the state-of-the-art (SOTA) LTE turbo decoder. As in conventional turbo decoding algorithms, the proposed Arbitrarily Parallel Turbo Decoder (APTD) decomposes each frame of information bits into a sequence of windows, where the bits within different windows are processed simultaneously using forward and backward recursions in a serial manner. However, in contrast to conventional turbo decoding algorithms, the APTD does not require different windows to be composed of an identical number of bits, which allows the use of an arbitrary number of windows and hence an arbitrary degree of parallelism, when decoding information bits of an arbitrary frame length. Furthermore, conventional turbo decoding algorithms alternate between simultaneously processing the windows in the upper decoder and those in the lower decoder. By contrast, the APTD processes the odd-indexed windows in the upper decoder at the same time as the even-indexed windows in the lower decoder and alternates between this and the reversed arrangement, hence further improving the decoding throughput and latency. Furthermore, the APTD achieves a reduced hardware resource requirement by calculating the extrinsic information based only on the outputs of the forward recursions, rather than based on both the forward and backward recursions of conventional turbo decoding algorithms. We demonstrate that the proposed APTD achieves superior latency, throughput, and computational efficiency than the SOTA LTE turbo decoder at all frame lengths, but particularly at the short frame lengths that are typically used in URLLC approaches. For example, at a frame length of N = 504 bits, the proposed APTD achieves an FER of 10-5at the same Eb/N0as I = 8 iterations of a conventional turbo decoder but with a computational efficiency that is 6 times higher than that of the SOTA turbo decoder, while achieving a latency and throughput that are 0.7 and 1.4 times those of the SOTA decoder, respectively.

Unary Error Correction (UEC) codes constitute a recently proposed Joint Source and Channel Code (JSCC) family, conceived for alphabets having an infinite cardinality, whilst out-performing previously used Separate Source and Channel Codes (SSCCs). UEC based schemes rely on an iterative decoding process, which involves three decoding blocks when concatenated with a turbo code. Owing to this, following the activation of one of the three blocks, the next block to be activated must be chosen from the other two decoding block options. Furthermore, the UEC decoder offers a number of decoding options, allowing its complexity and error correction capability to be dynamically adjusted. It has been shown that iterative decoding convergence can be expedited by activating the specific decoding option that offers the highest Mutual Information (MI) improvement to computational complexity ratio. This paper introduces an iterative demodulator, which is shown to improve the associated error correction performance, while reducing the overall iterative decoding complexity. The challenge is that the iterative demodulator has to forward its soft-information to the other two iterative decoding blocks, and hence the corresponding MI improvements cannot be compared on a like-for-like basis. Additionally, we also propose a method of eliminating the logarithmic calculations from the adaptive iterative decoding algorithm, hence further reducing its implementational complexity without impacting its error correcting performance.

Irregular joint source and channel coding (JSCC) scheme is proposed, which we refer to as the irregular unary error correction (IrUEC) code. This code operates on the basis of a single irregular trellis, instead of employing a set of separate regular trellises, as in previous irregular trellis-based codes. Our irregular trellis is designed with consideration of the UEC free distance, which we characterize for the first time in this paper. We conceive the serial concatenation of the proposed IrUEC code with an irregular unity rate code (IrURC) code and propose a new EXtrinsic Information Transfer (EXIT) chart matching algorithm for parametrizing these codes. This facilitates the creation of a narrow EXIT tunnel at a low Eb/N0value and provides near-capacity operation. Owing to this, our scheme is found to offer a low symbol error ratio (SER), which is within 0.4 dB of the discrete-input continuous-output memoryless channel (DCMC) capacity bound in a particular practical scenario, where gray-mapped quaternary phase shift keying (QPSK) modulation is employed for transmission over an uncorrelated narrowband Rayleigh-fading channel with an effective throughput of 0.508bits-1Hz-1. Furthermore, the proposed IrUEC-IrURC scheme offers a SER performance gain of 0.8 dB, compared to the best of several regular and irregular separate source and channel coding (SSCC) benchmarkers, which is achieved without any increase in transmission energy, bandwidth, transmit duration, or decoding complexity.