This paper proposes a technology mapping algorithm for implementing application circuits on via-switch FPGA (VS-FPGA). The via-switch is a novel non-volatile and rewritable memory element. Its small footprint and low parasitic RC are expected to improve the area- and energy-efficiency of an FPGA system. Some unique features of the VS-FPGA require a dedicated technology mapping strategy for implementing application circuits with maximum energy-efficiency. One of the features is the small ratio of logic blocks to arithmetic blocks (ABs). Given an application circuit, the proposed algorithm first detects word-wise circuit elements, such as MUXs. These elements are evaluated with an index of how resource utilization and fan-out change when the corresponding element is implemented with AB. All these elements are sorted in descending order based on this index. According to this order, each element is mapped to AB one by one, and synthesis and evaluation are repeated iteratively until satisfying given design constraints. The experimental results show that resource utilization and maximum fan-out can be reduced by about 30 % to 50 % and 12 % to 87 %, respectively. The proposed algorithm is not limited to the VS-FPGA and is expected to improve computation density and energy-efficiency of various FPGAs dedicated to compute-intensive signal processing applications.

This paper proposes a highly dense reconfigurable architecture that introduces via-switch device, which is a nonvolatile resistive-change switch and is used in crossbar switches. Via-switch is implemented in back-end-of-line layers only, and hence the front-end-of-line (FEoL) layers under the crossbar can be fully exploited for highly dense logic blocks. The proposed architecture uses the FEoL layers for fine-grained lookup tables and coarse-grained arithmetic/memory units for improving performance and compatibility with various applications. A case study of application mapping shows the proposed architecture can reduce the array area by 21.7%, thanks to the bidirectional interconnection. Thanks to F2footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by up to 26× and the delay and energy in the interconnection are reduced by 90% and 94% at 0.5-V operation.

This paper proposes a highly-dense reconfigurable architecture that introduces via-switch device, which is a kind of resistive RAM and is used in crossbar switches. Since via-switch is implemented in BEOL layers only, the FEOL layer under the crossbar can be fully exploited for highly-dense logic blocks. The proposed architecture uses the FEOL layer for fine-grained look-up tables and coarse-grained arithmetic/memory units for better performance and highly wide applications. In a case study of application mapping, the proposed architecture reduces array area by 76% thanks to mixed grained logic structure and overlay bidirectional interconnection. Thanks to 18F2footprint and one order of magnitude lower resistivity of via-switch compared to MOS switch, the crossbar density is improved by 26× and the delay and energy in the interconnection are reduced by 90% and 93% at 0.5V operation.

This paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.

This paper presents the realization of frequency-domain circuit analysis based on random walk framework for the first time. In conventional random walk based circuit analyses, the sample movement at a node is randomly chosen to follow the edge probabilities. The probabilities are determined by edge-admittances connecting to the node, which is impossible to apply for the frequency-domain analysis because the probabilities are imaginary numbers. By applying the idea of importance sampling, the intractable imaginary probabilities are converted into real numbers while maintaining the estimation correctness. Runtime acceleration through incremental analysis is also proposed.

This paper proposes a method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of an application circuit to a coarse-grained reconfigurable architecture (CGRA). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the features and parameters of each node in the DFG which characterize impact of the SEU in the node to the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.

Due to latest advances in semiconductor integration, systems are becoming more susceptible to faults leading to temporary or permanent failures. We propose a new architecture extension suitable for arrays of functional units (FUs), that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on data-path switching realized by the proposed hot-swapping algorithm and structures, by use of which functional units are tested and replaced by spares, at lower overheads than traditional modular redundancy. For a case study architecture, hot-swapping support could be added with only 29% area overhead. In this paper we focus on experimental evaluation of the hot-swapping system from a fabricated chip in 65nm CMOS process. Autonomous testing of the hot-swapping system is enhanced with back-bias circuitry to attain an early fault detection and restoration system. Experimental measurements prove that the proposed concept works well, predicting fault occurrence with a configurable prediction interval, while power measurements reveal that with only 20% power overhead the proposed system can attain reliability levels similar to triple modular redundancy. Additionally, measurements reveal that manufacturing randomness across the die can significantly influence identical sub-circuit reliability located in different parts in the die, although identical layout has been employed.

Power grid analysis for modern LSI is computationally challenging in terms of both runtime and memory usage. In this paper, we implement Krylov subspace based linear circuit solvers on a graphics processing unit (GPU) to realize fast power grid analysis. Efficiencies of memory space and access performance are pursued by improving a data structure that stores elements of large sparse matrices. Experimental results on benchmark circuits show that the proposed data structures are more suitable than widely used compressed sparse row (CSR) format and our GPU implementations can achieve up to 17x speedup over CPU implementations.

JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft Corporation. It supports high compression performance twice as high as the de facto image coding system, namely, JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In this article, we propose a novel architecture for JPEG XR encoding. In previous architectures, entropy coding was the throughput bottleneck because it was implemented as a sequential algorithm to handle data with dependency. We found that there is no dependency in intra-macroblock data, and we could safely pipeline all the encoding processes including the entropy coding. In addition, each module of our architecture, which can be regarded as a pipeline stage, can be parallelized. As a result, our architecture can achieve 12.8 pixel/cycle at its maximum. To demonstrate our architecture, we designed three versions of our architecture with different degrees of parallelism of one, two, and four. Our four-way parallel architecture achieves 579 Mpixel/sec at 181MHz clock frequency for grayscale images.

This paper proposes an importance sampling (IS) technique based on quasi-zero-variance estimation for accelerating convergence of random-walk-based power grid analysis. In our approach, the alternative probability for IS is incrementally updated after every Mr samples of random walk so that more recent and thus more accurate node voltages are utilized to asymptotically achieve ideal zero-variance estimation. We also propose a method to determine efficient Mr for the r-th probability update; although smaller Mr results more aggressive update of alternative probability, the alternative probability becomes inaccurate if Mr is too small. The estimation error of the proposed method decreases O((M/r)-r/2), which breaks O(M-1/2), the slow convergence-rate barrier of normal Monte Carlo analysis. Our trial implementation achieved 790x speedup compared with a conventional random-walk-based circuit analysis for analyzing IBM power grid benchmark circuits at 1mV accuracy.

In this paper, a significant acceleration of estimating low-failure rate in a high-dimensional SRAM yield analysis is achieved using sequential importance sampling. The proposed method systematically, autonomously, and adaptively explores failure region of interest, whereas all previous works needed to resort to brute-force search. Elimination of brute-force search and adaptive trial distribution significantly improves the efficiency of failure-rate estimation of hitherto unsolved high-dimensional cases wherein a lot of variation sources including threshold voltages, channel-length, carrier mobility, etc. are simultaneously considered. The proposed method is applicable to wide range of Monte Carlo simulation analyses dealing with high-dimensional problem of rare events. In SRAM yield estimation example, we achieved 106times acceleration compared to a standard Monte Carlo simulation for a failure probability of 3 × 10-9in a six-dimensional problem. The example of 24-dimensional analysis on which other methods are ineffective is also presented.

A novel technique that estimates on-chip process parameters, such as threshold voltages or channel length, is proposed. The proposed method is particularly useful as process condition estimator for reliability and yield enhancement techniques such as adaptive delay test or post-fabric performance compensation. Test paths consisting of a flip-flop and designated delay circuit, which is sensitive to individual process parameters, are inserted to obtain simultaneous delay inequalities. Then, the inequalities are solved for process parameters. The test path insertion is only on short paths to reduce delay and area overhead. Through numerical experiments, the proposed estimation flow using 150 paths achieve 10mV accuracy in estimating threshold voltages.

Adaptive test is one of the most efficient techniques that practically ensure high yield and reliability of designed chips. In this paper, a novel path-clustering method suitable for the adaptive test, in which test paths are altered according to the monitored process-parameters, is proposed. Considering the probability function of the die-to-die systematic process variation, the proposed method clusters path sets so that the total number of test-paths are minimized. For quantitative evaluation of different clusterings, figure of merit for clustering, which represents the expected number of test-paths at a particular test coverage, is also proposed. The proposed clustering is experimentally evaluated by applying to an industrial circuit. With our clustering, the average test paths in the adaptive test have been reduced to less than 50% compared with the ones of the conventional test.

This paper proposes a coarse-grained dynamically reconfigurable architecture, which offers flexible reliability to soft errors and aging. A notion of cluster is introduced as a basic element of the proposed architecture, each of which can select four operation modes with different levels of spatial redundancy and area-efficiency. Evaluation of permanent error rates demonstrates that four different reliability levels can be achieved by the proposed architecture. We also evaluate aging effect due to NBTI, and illustrate that alternating active cells with resting ones periodically will greatly mitigate the aging process with negligible power overhead. The area of additional circuits to attain immunity to soft errors and reliability configuration is 26.6% of the proposed reconfigurable device. Finally, a fault-tolerance evaluation of Viterbi decoder mapped on the proposed architecture suggests that there is a considerable trade-off between reliability and area overhead.

Due to latest advances in semiconductor integration, systems are becoming more susceptible to faults leading to temporary or permanent failures. We propose a new architecture extension suitable for arrays of functional units, that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on data path switching controlled by a hot-swapping algorithm, by use of which functional units are tested and replaced by spares if necessary, ensuring permanent operation while the spares last. The Hot-Swapping functionality could be added as a case study on a sample architecture, with an overhead of 74-87%. Also, a prototype chip (4.2 mm times 2.1 mm) targeted to operate at 166 MHz has been fabricated, using 65 nm process technology.

Emerging high-speed mobile networks enable us to receive media streaming data by mobile terminals on demand. However, media streaming with fixed bitrate causes some problems such as annoying artificial noise, interruption, and so forth, since link quality fluctuates dramatically in such mobile networks. Motivated by this, in this paper, we propose a novel media streaming system with dynamic rate control scheme to achieve continuous streaming on such unstable networks. The proposed rate control scheme uses the delay of the transcoding process to estimate network bandwidth, and adjusts the bitrate of media streams dynamically. To demonstrate our system and scheme, the proposed streaming system is evaluated under some typical models of bandwidth change in high-speed mobile networks. The results show that stable and high-quality streaming without interruption can be achieved by the proposed scheme. Moreover, we successfully demonstrate that our system performs continuous streaming on real mobile networks even in the severe network condition such as on a moving train.

In this paper, a prototype implementation of stream- ing system that allows listening to and viewing multimedia contents using a mobile terminal, as part of our efforts toward realizing services linked with home networks and mobile net- works is presented. In our system, appliances are detected and connected to a mobile terminal by use of peer-to-peer (P2P) network based on the PUCC protocols, and they are controlled by use of P2P messages and IEEE1394 AV/C. Streaming is managed by a gateway on the P2P network, where multimedia contents are converted to another format suitable to be sent to mobile terminals. This prototype system successfully achieves video data streaming over two different networks by using P2P network which conceals the differences among the networks.

Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from memory bit upsets caused by charged particles in space that result in fatal system troubles.This paper proposes an autonomous repair mechanism against configuration upsets for fault-tolerant reconfigurable devices. In proposed architecture, devices consist of 'Autonomous-Repair Cells' with built-in (not reprogrammable) error recovery circuits. Each cell realizes a part of the system's functionality, and guarantees fault tolerance against upset of its own configuration memory. In this paper, four types of Autonomous-Repair Cells are designed and then average lifetime is analyzed. Two of cells are based on TMR (Triple Module Redundancy) and the others are based on EDAC (Error Detection and Correction). In a severe situation where a conventional reconfigurable device with 1Mbit configuration data can achieve only 1-minute average lifetime against configuration upsets, all proposed cells can achieve more than 100 years.

Reconfigurable devices are expected to be utilized in the mission-critical fields such as space development, because a system update and a pseudo-repair can be achieved remotely by reconfiguration. However, conventional reconfigurable devices suffer from configuration memory upsets caused by radiation in space. This paper proposes an architecture of a fault-tolerant reconfigurable device based on island-style FPGA. The device consists of "autonomous-repair cells" which repairs these upsets autonomously and dynamically. To determine the architecture, we analyze four autonomous repair techniques of the cell experimentally. Then, optimal autonomous repair techniques are applied to both of programmable logics and cell-to-cell routing resources. Through evaluation, we show that proposed device achieves more than 10 years average lifetime against configuration upsets even in a severe situation such as a satellite orbit

An encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process entropy encoding/decoding. This module, however, requests many small-size memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory architecture of the entropy encoding/decoding module is proposed, in which three approaches are attempted by utilizing one-bank SRAMs and internal registers. As a result, the efficient memory organization for a target process technology can be explored

No abstract available.

The paper presents an efficient method for manipulating very large shared binary decision diagrams (SBDDs) which are too large to be stored within main memory. In contrast that the conventional depth-first algorithm causes random access of memory, the proposed method is intended to cause sequential access of memory. The main idea of our method is level-by-level manipulation of shared quasi-reduced BDD's (SQBDD's) upon a breadth-first algorithm. A garbage collection algorithm based on sliding type compaction is also introduced in order to reduce page faults in succeeding manipulation. We implemented and evaluated the proposed method on the workstation Sun SPARC Station 10 and 64 Mbyte main memory and a 1 Gbyte hard disk drive. As a result it took only 5.6 h to obtain an SQBDD of more than 12 million nodes, which represents all the primary outputs of a 15-bit multiplier, from its circuit description. If we use the conventional SBDD manipulator instead, it is estimated that it would take about 1900 h.

Boolean function manipulators based on Shared Binary Decision Diagrams (SBDD'S) =e utilized efficiently in various applications such as design verification.We propose a high-speed algorithm of manipulating SBDD'S, which can be used with a vector supercomputer effectively.This proposed algorithm is implement ed and evaluated on the vector supercomput er HI-TAC S-820/80.The vector acceleration ratio obtained is 14.3 in the best case. 1