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Subramanian K. Iyer

dblp:16/3548 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 3 · 1 first-authorTheory of computation · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
2 papers
Automated reasoning and model checking · 77% Computational geometry · 23%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Parallel and multicore computing · 13%
Software engineering, system software, and programming languages
1 paper
Program verification · 100%

Topics — the 5 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Automated reasoning and model checking › model checking
symbolic model checking
0.122006
On partitioning and symbolic model checking · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
On Partitioning and Symbolic Model Checking · FM 2005
Electronic design automation
hardware verification and test
0.112005
Multi-threaded reachability · DAC 2005
Electronic design automation › hardware verification and test › formal verification
reachability analysis
0.112005
Multi-threaded reachability · DAC 2005
Computational geometry
partitioning
0.112005
On Partitioning and Symbolic Model Checking · FM 2005
Parallel and multicore computing › parallel computing › parallel program analysis
parallel verification
0.012005
Multi-threaded reachability · DAC 2005

Methods — techniques the papers use, named apart from their topics

partitioned model checking · 0.1crossover image computation · 0.1partitioned BDD · 0.1multithreading · 0.1
YearPublicationVenuePosition
2006 On partitioning and symbolic model checking
abstract
State-space-partitioning-based approaches have been proposed in the literature to address the state-explosion problem in model checking. These approaches, whether sequential or distributed, perform a large amount of work in the form of interpartition (crossover) image computations, which can be expensive. A model-checking algorithm that aggregates these expensive crossover images by localizing computation to individual partitions is presented. It reduces the number of crossover images and drastically outperforms extant approaches in terms of crossover image computation cost as well as total model-checking time, often by two orders of magnitude.
Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2005 Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes
abstract
Formal verification, especially error detection, is rapidly increasing in importance with the rising complexity of designs. The main constraint in verification is the total amount of resources available - both time as well as memory. Most attempts at verification only use a single processor. Recently, various attempts have been made to use parallel and distributed methods for verification. However, verification in a Grid-based environment has not yet been very widely adopted. As personal computers gain in computing capacity, the concept of computation grids is gaining acceptance. Here, a grid is a network of machines that may not be dedicated to a specific computational use, but may only be available some of the time. This is a unique environment where massive parallelism is possible by using otherwise idle CPU cycles from a large number of computers. Such processors may even be in geographically diverse locations. We describe a Grid-based verifi- cation environment for detecting errors in a design. We verify user-written assertions as well as properties, e.g. unreachable code, index-out-of-range, that are extracted automatically from the design using a state-of-the-art HDL parser. Such an approach can help the user to quickly find RTL level bugs earlier in the design cycle.
Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu
Asian Test Symposium1
2005 A New Reachability Algorithm for Symmetric Multi-processor Architecture
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill
ATVA3
2005 Multi-threaded reachability
abstract
Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. Such algorithms can be at times ineffective as they suffer from the problem of scheduling the relative order in which the partitions are processed. In this paper we present a novel multi-threaded reachability algorithm that avoids this scheduling problem while increasing the latent parallelism in partitioned state space traversal. We show that in most cases our method is significantly faster than both the standard reachability algorithm as well as the existing partitioned approaches. The gains are further magnified when our threaded implementation is evaluated in the context of a parallel framework.
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
DAC3
2005 On Partitioning and Symbolic Model Checking
Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
FM1
2004 A Partitioning Methodology for BDD-Based Verification
Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
FMCAD2