Single-electron devices have been widely used in electronics and physics research, and are believed to be one of the potential alternatives to CMOS circuits due to their small size and ultra-low power dissipation. In the recent past, three simulation methods have been used for single-electron device and circuit analysis: the Monte Carlo method, the master equation method, and SPICE using analytic models. Among these, the Monte Carlo method provides excellent accuracy, but is too slow for large-scale circuit simulation. In this work, we propose and develop an adaptive simulation technique based on the Monte Carlo method. This technique significantly improves the time efficiency while maintaining accuracy for single-electron device and circuit simulation. We have shown it is possible to reduce simulation time up to nearly 40 times and maintain an average propagation delay error of 3.4% compared to a nonadaptive Monte Carlo method.

Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultra-low-power designs may even permit embedded systems to operate without batteries by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation. Recent developments in nanoscale devices open new alternatives for low-power embedded system design. Among these, single-electron tunneling transistors (SETs) hold the promise of achieving the lowest power consumption. Unfortunately, most analysis of SETs has focused on single devices instead of architectures, making it difficult to determine whether they are appropriate for low-power embedded systems. Evaluating the use of SETs in large-scale digital systems requires novel architectural and circuit design. SET-based design imposes numerous challenges resulting from low driving strength, relatively large static power consumption, and the presence of reliability problems resulting from random background charge effects. We propose a fault-tolerant, hybrid SET/CMOS, reconfigurable architecture, named IceFlex, that can be tailored to specific requirements and allows tradeoffs among power consumption, performance requirements, operation temperature, fabrication cost, and reliability. Using IceFlex as a testbed, we characterize the benefits and limitations of SETs in embedded system designs. In particular, we focus on the use of SETs in room-temperature ultra-low-power embedded systems such as wireless sensor network nodes. We also consider high-performance applications such as multimedia consumer electronics. We see this work as a first step in determining the potential of ultra-low-power embedded system design using SETs.

Single-electron devices have drawn much attention in the last two decades. They have been widely used for device research and also show promise as a potential alternative to complementary metal-oxide- semiconductor circuits due to their ultra low power dissipation. Three techniques have been used for single-electron device modeling in the past, including Monte Carlo simulation, master equation, and SPICE modeling. Among these, Monte Carlo method provides accuracy, but lacks the time efficiency required for large scale simulation. In this work, we introduce an adaptive multi-scale approach to single- electron device simulation using Monte Carlo method as basis, which significantly improves time efficiency while maintaining accuracy. We have shown it is possible to reduce simulation time up to 40 times and maintain an average error of 3.3% compared to non-adaptive Monte Carlo method. Going beyond simplistic approximations, we have modeled important secondary effects including cotunneling and Cooper pair tunneling, which are critical for device research.

Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultra-low-power designs may even permit embedded systems to operate without batteries, e.g., by scavenging energy from the environment. Moreover, managing power dissipation is now a key factor in integrated circuit packaging and cooling. As a result, embedded system price, size, weight, and reliability are all strongly dependent on power dissipation.