This paper proposes a complete and full automation framework of evaluating design rules (DRs) to facilitate the process of design technology co-optimization (DTCO), which is highly demanded in 14-nm and beyond technologies. Our proposed framework explores the changes of DRs and evaluates the impacts on the number and types of DR violations as well as the resulting cell/chip layout area. Precisely, the core engine of our DR evaluation framework for DTCO, the automatic cell layout generator, consists of key enabling techniques for standard cell layout optimization. They are integrated coherently to seamlessly support the advanced process technologies using FinFET transistors, complex DRs, and double patterning (DP) lithography. Also, the tight integration of our automatic cell layout generation into the DR evaluation framework with diverse analysis features enables the DTCO process to be much faster and more efficient. We provide a set of experimental data not only to show how much our proposed enabling techniques are effective in optimizing layouts but also to show how effectively our framework explores and analyzes the DTCO parameters (e.g., ground DRs and DP DRs).

This work addresses the problem of automatically synthesizing compact standard cell layouts with 2D metal-1 routing under design rule constraints. Precisely, we propose a set of new highly impacting techniques dedicated solely to the generation of cell layouts with 2D metal-1 routing completion. Those are (1) netlist decomposition (2) transistor chaining combined with transistor folding, (3) gate poly ordering combined with fast routing congestion estimation, and (4) 2D single-layer routing with minimal resource. It is shown from experiments that our proposed layout generator is able to produce layouts of quality comparable to the expert's manual ones, but spending just one hour for 56 representative cells generation.

The portion of clock power in system is rapidly increasing with the continuous increasing of clock frequency and clock resources. Last two decades, a great research attention has been paid to minimizing the clock power. Recently, it is shown that the structure of resonant clock networks is very effective in saving power since it can store electric energy to the inserted inductors rather than dissipate. On the other side, it has been known that dynamic voltage-frequency scaling (DVFS) is one of the most effectively and widely used power reduction techniques. However, so far no works have addressed the design methodology problem of synthesizing resonant clock networks that are able to operate under the designs with DVFS capability even though the problem is potentially very important to maximize the synergy effect on saving power. In this context, this paper proposes a comprehensive solution to the problem. Precisely, we propose a two-phase synthesis algorithm: 1) formulating the problem of inductor allocation, placement, and adjustable-sizing to support DVFS into a weighted set cover problem with the objective of minimizing total area of inductors and 2) followed by performing the task of resizing of adjustable driving buffers to support the switch of driving strength according to the clock frequencies by DVFS. Through experiments with benchmark circuits, it is shown that for designs with DVFS using 1 and 3 GHz, our algorithm synthesizes resonant clock networks with 25.9% less power on the execution of the clock frequency, which is not supported by resonant clocking in the previous no-DVFS aware resonant clock synthesis algorithm.

The portion of clock power in system is rapidly increasing with the continuous increasing of clock frequency and clock resources. Last two decades, a great research attention has been paid to minimizing the clock power. Recently, it is shown that the structure of resonant clock networks is very effective in saving power since it can store electric energy to the inserted inductors rather than dissipate. On the other side, it has been known that dynamic voltage-frequency scaling (DVFS) is one of the most effectively and widely used power reduction techniques. However, so far no works have addressed the problem of synthesizing resonant clock networks that are able to operate under the designs with DVFS capability even though the problem is potentially very important to maximize the synergy effect on saving power. In this context, this work proposes a comprehensive solution to the problem. Precisely, we propose a two-phase synthesis algorithm: (1) formulating the problem of inductor allocation, placement, and adjustable-sizing to support DVFS into a weighted set cover problem with the objective of minimizing total area of inductors followed by (2) performing the task of resizing of adjustable driving buffers to support the switch of driving strength according to the clock frequencies by DVFS. Through experiments with benchmark circuits, it is shown that for designs with DVFS using 1GHz and 3GHz, our algorithm synthesizes resonant clock networks with 17% less power on the execution of the clock frequency, which is not supported by resonant clocking in the previous no-DVFS aware resonant clock synthesis algorithm.