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J. K. Singh

dblp:161/6755 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
semiconductor device fabrication		 0.021987
Dependence of process parameters on planarization isolation and etching of sloped vias in polyimides for GaAs ICs · Proc. IEEE 1987
Near state-of-the-art power in p+-n-n+D-band IMPATT diode on a wafer with ramped n-n+interface · Proc. IEEE 1987
Integrated circuit design › semiconductor devices › diode
IMPATT diode		 0.011987
Near state-of-the-art power in p+-n-n+D-band IMPATT diode on a wafer with ramped n-n+interface · Proc. IEEE 1987

Methods — techniques the papers use, named apart from their topics

resistive heating · 0.0imidization · 0.0diffusion · 0.0chemical etching · 0.0
YearPublicationVenuePosition
1987 Near state-of-the-art power in p+-n-n+D-band IMPATT diode on a wafer with ramped n-n+interface
abstract
Fabrication of near state-of-the-art (P0= 110 mW, η = 4.85 percent p+-n-n+D band (f = 124 GHz) Si IMPATT diode on a wafer with ramped n-n+interface is described. Introduction of a critical annealing step, prior to p+diffusion, in the fabrication sequence of the diode has been found to yield the above results. Possible reasons for power and efficiency enhancement has been discussed.
J. K. Singh, H. S. Gokgor, A. M. Howard, F. A. Myers
 Proc. IEEE1
1987 Dependence of process parameters on planarization isolation and etching of sloped vias in polyimides for GaAs ICs
abstract
The effect of imidization condition for realizing sloped vias in polyimide film using positive resist as an etch mask has been investigated. Using chemical etching techniques, vias of tapered angles ranging from 45° to 60° has been obtained for 80-percent imidization of the polyimide film. Results on optimum process conditions for obtaining dielectric breakdown strength of 2MV/cm and degree of planarization of about 58 percent have also been included.
J. K. Singh, A. Roybardhan, H. S. Kothari, Babu R. Singh, W. S. Khokle
 Proc. IEEE1