Conventional telecommunication techniques are optimized to communicate over long distances (>1 mi), subject to high attenuation, high crosstalk, and other deteriorations in transmission. A trend in telecommunication system architectures is to disperse the previously centralized switching centers, thereby providing switching within a few hundred feet of the subscriber. This creates an opportunity for great improvements in cost and performance for short distance communication links. A technique for low-power digital communication over short transmission lines that exploits this possibility is described. The typical power is more than an order of magnitude lower than the power required with conventional circuits. Associated with this technique are a tenfold reduction in the chip area occupied by the transmission line drivers and the elimination of coupling transformers. The power and chip-area reductions result from terminating and maintaining an open circuit at the receiver. These advantages make this line-driving technique particularly suitable for single-chip VLSI systems.>

A complete set of tunnel-diode logic circuits has been developed. The average delay per logic level is 0.5 nsec (0.5×10-9sec). The average dc power dissipation per gate is 100 mw (other gate properties are given in Table I). In order to achieve this Performance, the following new techniques were employed: 1) nonlinear biasing using the tunnel resistor, a new tunneling device; 2) trimming, a technique of current bias adjustment to offset initial tolerances; 3) transmission-line terminating without sacrificing signal amplitude. Using these circuits, a 40-gate model was constructed which is capable of shifting and counting at a rate of 300 Mc. This model has been in operation for approximately 2000 hours with very good reliability.