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R. Brainard

dblp:165/3659 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Image and video coding · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Image and video coding › predictive coding
differential pulse code modulation
0.011987
VLSI Implementation of a DPCM Compression Algorithm for Digital TV · IEEE Trans. Commun. 1987
Image and video coding
predictive coding
0.011987
VLSI Implementation of a DPCM Compression Algorithm for Digital TV · IEEE Trans. Commun. 1987
Image and video coding
VLSI implementation
0.011987
VLSI Implementation of a DPCM Compression Algorithm for Digital TV · IEEE Trans. Commun. 1987

Methods — techniques the papers use, named apart from their topics

TTL logic implementation · 0.0
YearPublicationVenuePosition
1987 VLSI Implementation of a DPCM Compression Algorithm for Digital TV
abstract
Future video services in the loop plant may be based on digital transmission through optical fibers. A small and inexpensive codec is required for a variety of services based on digital television. We have demonstrated a compression algorithm for transmission of NTSC color television over a DS3 channel (44.736 Mbits/s). This predictive coding algorithm has been implemented using circuits built with conventional TTL logic. The resulting picture is visually unimpaired, but may not have network quality. The major portion of the compression or reconstruction circuit has also been implemented in one CMOS VLSI chip. Compression is accomplished using this chip with two small ROM chips. Reconstruction is done with the same VLSI chip and one ROM chip.
R. Brainard, Joseph H. Othmer
IEEE Trans. Commun.1