Demo Data from SIGIR 2026 / reviewers in the wild / expert
Oleksii Oleksenko
dblp:166/4142
· DBLP profile ↗
13ranked-venue papers
5as first author
5since 2021 · last 2025
0009-0009-1964-8038ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 8 · 3 first-author · 2 since 2021Security and privacy · 6 · 3 first-author · 3 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021Artificial intelligence and machine learning · 1Databases, data management, data science and information retrieval · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
8 papers |
Hardware security and side channels · 90% Systems and software security · 10% | |
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Processor architecture and microarchitecture · 70% Electronic design automation · 24% Cloud and datacenter computing · 6% |
Topics — the 24 heaviest of 24, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels › microarchitectural attacks › transient execution attack
speculative execution attack |
1.4 | 2 | 2025 | AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures · ASPLOS (2) 2025 Revizor: testing black-box CPUs against speculation contracts · ASPLOS 2022 |
Processor architecture and microarchitecture
speculative execution |
1.2 | 2 | 2023 | Hide and Seek with Spectres: Efficient discovery of speculative information leaks with random testing · SP 2023 Revizor: testing black-box CPUs against speculation contracts · ASPLOS 2022 |
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre defense |
0.9 | 1 | 2025 | AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures · ASPLOS (2) 2025 |
Electronic design automation
hardware verification and test |
0.9 | 1 | 2025 | AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures · ASPLOS (2) 2025 |
Hardware security and side channels › side-channel countermeasures
microarchitectural side-channel defense |
0.8 | 1 | 2024 | Principled Microarchitectural Isolation on Cloud CPUs · CCS 2024 |
Hardware security and side channels
microarchitectural attacks |
0.7 | 1 | 2023 | Hide and Seek with Spectres: Efficient discovery of speculative information leaks with random testing · SP 2023 |
Hardware security and side channels › microarchitectural side channel
microarchitectural leakage |
0.7 | 1 | 2023 | Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions · USENIX Security Symposium 2023 |
Hardware security and side channels › microarchitectural attacks
speculative execution leakage |
0.7 | 1 | 2023 | Hide and Seek with Spectres: Efficient discovery of speculative information leaks with random testing · SP 2023 |
Processor architecture and microarchitecture › microarchitectural security
transient execution attacks |
0.7 | 1 | 2023 | Hide and Seek with Spectres: Efficient discovery of speculative information leaks with random testing · SP 2023 |
Hardware security and side channels
trusted execution environments |
0.6 | 2 | 2018 | Varys: Protecting SGX Enclaves from Practical Side-Channel Attacks · USENIX ATC 2018 SGXBOUNDS: Memory Safety for Shielded Execution · EuroSys 2017 |
Hardware security and side channels › microarchitectural attacks › transient execution attack › speculative execution attack
spectre |
0.6 | 1 | 2022 | Revizor: testing black-box CPUs against speculation contracts · ASPLOS 2022 |
Hardware security and side channels › side channel
speculative execution vulnerabilities |
0.4 | 1 | 2020 | SpecFuzz: Bringing Spectre-type vulnerabilities to the surface · USENIX Security Symposium 2020 |
Systems and software security
vulnerability discovery |
0.4 | 1 | 2020 | SpecFuzz: Bringing Spectre-type vulnerabilities to the surface · USENIX Security Symposium 2020 |
Hardware security and side channels › trusted execution environments
Intel SGX |
0.3 | 1 | 2017 | SGXBOUNDS: Memory Safety for Shielded Execution · EuroSys 2017 |
Systems and software security
memory safety |
0.3 | 1 | 2017 | SGXBOUNDS: Memory Safety for Shielded Execution · EuroSys 2017 |
Hardware security and side channels › trusted execution environments
shielded execution |
0.3 | 1 | 2017 | SGXBOUNDS: Memory Safety for Shielded Execution · EuroSys 2017 |
Processor architecture and microarchitecture › speculative execution
secure speculation |
0.3 | 1 | 2025 | AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures · ASPLOS (2) 2025 |
Cloud and datacenter computing
virtualization |
0.2 | 1 | 2024 | Principled Microarchitectural Isolation on Cloud CPUs · CCS 2024 |
Processor architecture and microarchitecture
speculation |
0.2 | 1 | 2023 | Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions · USENIX Security Symposium 2023 |
Processor architecture and microarchitecture › speculative execution
transient execution |
0.2 | 1 | 2023 | Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions · USENIX Security Symposium 2023 |
Software testing
black-box testing |
0.2 | 1 | 2022 | Revizor: testing black-box CPUs against speculation contracts · ASPLOS 2022 |
Software testing
fuzzing |
0.1 | 1 | 2020 | SpecFuzz: Bringing Spectre-type vulnerabilities to the surface · USENIX Security Symposium 2020 |
Systems and software security › trusted computing
enclave security |
0.1 | 1 | 2018 | Varys: Protecting SGX Enclaves from Practical Side-Channel Attacks · USENIX ATC 2018 |
Hardware security and side channels › hardware attacks
side-channel and fault attacks |
0.1 | 1 | 2017 | SGXBOUNDS: Memory Safety for Shielded Execution · EuroSys 2017 |
Methods — techniques the papers use, named apart from their topics
fuzzing · 2.2automated design-time testing · 1.7speculation contracts · 1.7differential testing · 1.7isolation contracts · 1.5testing · 1.3random testing · 1.3modeling · 1.3sanitizers · 0.9memory-safety enforcement · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | AMuLeT: Automated Design-Time Testing of Secure Speculation CountermeasuresabstractIn recent years, several hardware-based countermeasures proposed to mitigate Spectre attacks have been shown to be insecure. To enable the development of effective secure speculation countermeasures, we need easy-to-use tools that can automatically test their security guarantees early-on in the design phase to facilitate rapid prototyping. Leo Tenenbaum, David Adler, Assaf Klein, Arpit Gogia, Alaa R. Alameldeen, Marco Guarnieri, Mark Silberstein, Oleksii Oleksenko, Gururaj Saileshwar |
ASPLOS (2) | 9 |
| 2024 | Principled Microarchitectural Isolation on Cloud CPUsabstractWe present Marghera, a system design that prevents cross-VM microarchitectural side-channel attacks in the cloud. Marghera is based on isolation contracts which, for a given CPU, describe partitions of physical threads and memory that prevent information leakage through shared microarchitectural resources. Stavros Volos, Cédric Fournet, Jana Hofmann, Boris Köpf, Oleksii Oleksenko |
CCS | 5 |
| 2023 | Hide and Seek with Spectres: Efficient discovery of speculative information leaks with random testingabstractAttacks like Spectre abuse speculative execution, one of the key performance optimizations of modern CPUs. Recently, several testing tools have emerged to automatically detect speculative leaks in commercial (black-box) CPUs. However, the testing process is still slow, which has hindered in-depth testing campaigns, and so far prevented the discovery of new classes of leakage.In this paper, we identify the root causes of the performance limitations in existing approaches, and propose techniques to overcome these limitations. With these techniques, we improve the testing speed over the state-of-the-art by up to two orders of magnitude.These improvements enable us to run a testing campaign of unprecedented depth on Intel and AMD CPUs. As a highlight, we discover two types of previously unknown speculative leaks (affecting string comparison and division) that have escaped previous manual and automatic analyses. Oleksii Oleksenko, Marco Guarnieri, Boris Köpf, Mark Silberstein |
SP | 1 |
| 2023 | Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions
Jana Hofmann, Emanuele Vannacci, Cédric Fournet, Boris Köpf, Oleksii Oleksenko |
USENIX Security Symposium | 5 |
| 2022 | Revizor: testing black-box CPUs against speculation contractsabstractSpeculative vulnerabilities such as Spectre and Meltdown expose speculative execution state that can be exploited to leak information across security domains via side-channels. Such vulnerabilities often stay undetected for a long time as we lack the tools for systematic testing of CPUs to find them. Oleksii Oleksenko, Christof Fetzer, Boris Köpf, Mark Silberstein |
ASPLOS | 1 |
| 2020 | T-Lease: a trusted lease primitive for distributed systemsabstractA lease is an important primitive for building distributed protocols, and it is ubiquitously employed in distributed systems. However, the scope of the classic lease abstraction is restricted to the trusted computing infrastructure. Unfortunately, this important primitive cannot be employed in the untrusted computing infrastructure because the trusted execution environments (TEEs) do not provide a trusted time source. In the untrusted environment, an adversary can easily manipulate the system clock to violate the correctness properties of lease-based systems. Bohdan Trach, Rasha Faqeh, Oleksii Oleksenko, Wojciech Ozga, Pramod Bhatotia, Christof Fetzer |
SoCC | 3 |
| 2020 | SpecFuzz: Bringing Spectre-type vulnerabilities to the surface
Oleksii Oleksenko, Bohdan Trach, Mark Silberstein, Christof Fetzer |
USENIX Security Symposium | 1 |
| 2019 | Clemmys: towards secure remote execution in FaaSabstractWe introduce Clemmys, a security-first serverless platform that ensures confidentiality and integrity of users' functions and data as they are processed on untrusted cloud premises, while keeping the cost of protection low. We provide a design for hardening FaaS platforms with Intel SGX---a hardware-based shielded execution technology. We explain the protocol that our system uses to ensure confidentiality and integrity of data, and integrity of function chains. To overcome performance and latency issues that are inherent in SGX applications, we apply several SGX-specific optimizations to the runtime system: we use SGXv2 to speed up the enclave startup and perform batch EPC augmentation. To evaluate our approach, we implement our design over Apache Open-Whisk, a popular serverless platform. Lastly, we show that Clemmys achieved same throughput and similar latency as native Apache OpenWhisk, while allowing it to withstand several new attack vectors. Bohdan Trach, Oleksii Oleksenko, Franz Gregor, Pramod Bhatotia, Christof Fetzer |
SYSTOR | 2 |
| 2018 | Varys: Protecting SGX Enclaves from Practical Side-Channel Attacks
Oleksii Oleksenko, Bohdan Trach, Robert Krahn, Mark Silberstein, Christof Fetzer |
USENIX ATC | 1 |
| 2017 | Fex: A Software Systems EvaluatorabstractSoftware systems research relies on experimental evaluation to assess the effectiveness of newly developed solutions. However, the existing evaluation frameworks are rigid (do not allow creation of new experiments), often simplistic (may not reveal issues that appear in real-world applications), and can be inconsistent (do not guarantee reproducibility of experiments across platforms). This paper presents Fex, a software systems evaluation framework that addresses these limitations. Fex is extensible (can be easily extended with custom experiment types), practical (supports composition of different benchmark suites and real-world applications), and reproducible (it is built on container technology to guarantee the same software stack across platforms). We show that Fex achieves these design goals with minimal end-user effort - for instance, adding Nginx web-server to evaluation requires only 160 LoC. Going forward, we discuss the architecture of the framework, explain its interface, show common usage scenarios, and evaluate the efforts for writing various custom extensions. Oleksii Oleksenko, Dmitrii Kuvaiskii, Pramod Bhatotia, Christof Fetzer |
DSN | 1 |
| 2017 | SGXBOUNDS: Memory Safety for Shielded ExecutionabstractShielded execution based on Intel SGX provides strong security guarantees for legacy applications running on untrusted platforms. However, memory safety attacks such as Heartbleed can render the confidentiality and integrity properties of shielded execution completely ineffective. To prevent these attacks, the state-of-the-art memory-safety approaches can be used in the context of shielded execution. Dmitrii Kuvaiskii, Oleksii Oleksenko, Sergei Arnautov, Bohdan Trach, Pramod Bhatotia, Pascal Felber, Christof Fetzer |
EuroSys | 2 |
| 2016 | ELZAR: Triple Modular Redundancy Using Intel AVX (Practical Experience Report)abstractInstruction-Level Redundancy (ILR) is a well-known approach to tolerate transient CPU faults. It replicates instructions in a program and inserts periodic checks to detect and correct CPU faults using majority voting, which essentially requires three copies of each instruction and leads to high performance overheads. As SIMD technology can operate simultaneously on several copies of the data, it appears to be a good candidate for decreasing these overheads. To verify this hypothesis, we propose ELZAR, a compiler framework that transforms unmodified multithreaded applications to support triple modular redundancy using Intel AVX extensions for vectorization. Our experience with several benchmark suites and real-world case-studies yields mixed results: while SIMD may be beneficial for some workloads, e.g., CPU-intensive ones with many floating-point operations, it exposes higher overhead than ILR in many applications we tested. Dmitrii Kuvaiskii, Oleksii Oleksenko, Pramod Bhatotia, Pascal Felber, Christof Fetzer |
DSN | 2 |
| 2015 | Resiliency-aware Data Compression for In-memory Database SystemsabstractNowadays, database systems pursuit a main memory-centric architecture, where the entire business-related
data is stored and processed in a compressed form in main memory. In this case, the performance gain is
massive because database operations can benefit from its higher bandwidth and lower latency. However,
current main memory-centric database systems utilize general-purpose error detection and correction solutions
to address the emerging problem of increasing dynamic error rate of main memory. The costs of these generalpurpose
methods dramatically increases with increasing error rates. To reduce these costs, we have to exploit
context knowledge of database systems for resiliency. Therefore, we introduce our vision of resiliency-aware
data compression in this paper, where we want to exploit the benefits of both fields in an integrated approach
with low performance and memory overhead. In detail, we present and evaluate a first approach using AN
encoding and two different compression schemes to show the potentials and challenges of our vision. Till Kolditz, Dirk Habich, Patrick Damme, Wolfgang Lehner, Dmitrii Kuvaiskii, Oleksii Oleksenko, Christof Fetzer |
DATA | 6 |