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Paul T. Greiling

dblp:167/4835 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
high-speed digital circuits
0.011985
The Future Impact of GaAs Digital IC's · IEEE J. Sel. Areas Commun. 1985
Integrated circuit design › high-speed integrated circuits › high-speed integrated circuit design
high-speed interface circuits
0.011985
The Future Impact of GaAs Digital IC's · IEEE J. Sel. Areas Commun. 1985
Integrated circuit design
low-power circuit design
0.011985
The Future Impact of GaAs Digital IC's · IEEE J. Sel. Areas Commun. 1985

Methods — techniques the papers use, named apart from their topics

review · 0.0
YearPublicationVenuePosition
1985 The Future Impact of GaAs Digital IC's
abstract
A review of digital GaAs IC technology and an assessment of its future impact on gigabit signal processing is presented. High-speed signal processing and computers will require MSI-complexity interface circuits capable of 1-10 GHz clock frequencies and LSI-complexity digital circuits operating in the 0.2-5 GHz range at tens of microwatts per gate. A wide range of applications exists for frequency counters, multiplexers, A/D converters, FFT's, microprocessors, and memories that operate at speeds significantly higher than on presently available circuits. Issues related to high-speed IC design such as power dissipation, packing density, capacitance effects, design rules, and intra- and interchip propagation delays are discussed.
Paul T. Greiling
IEEE J. Sel. Areas Commun.1